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ATPL100A Datasheet(PDF) 3 Page - ATMEL Corporation

Part # ATPL100A
Description  FSK Power Line Communications SoC
PDF  10 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATPL100A Datasheet(HTML) 3 Page - ATMEL Corporation

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Atmel ATPL100A [Summary datasheet]
43002A-ATPL-03/12
3
1.
Block Diagram
Figure 1-1. ATPL100A 144-pin Block Diagram
JTAG
Bscan
DEBUG
RESET
Clock
Reset
Interface
Clock
Interface
Power
Management
CODE
SRAM
BOOT
LOADER
SPI0
XDATA
SRAM
SPI1
UART0
UART1
UART2
TIMER0
TIMER1
TIMER2
T11, T12, T14
WATCHDOG
GENERAL
PURPOSE I/O
DIMMER
PERIPHERAL
LCD DRIVER
MEDIUM
ACCESS
CONTROL
VSENSE
PSENSE
EMIT(12:0)
ENABLE
DC_COMP
D_IN
D_NIN
REC(8:1)
VIN
VRH
VRL
8051C3A Core
PLC
MODEM
M
U
X
IDATA
128KB SRAM
SEGM(23:20)
SEGM(19:0)
BCKP(7:4)
BCKP(3:0)
TRIAC_(3:0)
VNR
D_INIT
RSTA
CLKA
CLKB
MISO, MOSI,
CLK, SS
Rx0, Tx0
Rx1, Tx1
Rx2, Tx2
T0
T1
T2
T2EX
VDD
VSSO
LDO_PD
VDEO
INTA(3:0)
INTB(3:0)
INTC(3:0)
INTD(3:0)
AVD
AVS
TDI
TDO
TCK
TMS
TRST
/EWDG
DEBUG
/PROG
SECURED
SSN
11.059.200Hz
INT1
P1.7
P3(1,2), P3(3:5)
P4(0:7)
P5(0:5)
MISO1, MOSI1,
CLK1, SS1



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