AP3984 datasheet(9/15 Pages) DIODES

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AP3984

Document number: DS37655 Rev. 3 - 2

9 of 15

www.diodes.com

December 2016

AP3984

Operation Description (Cont.)

During AM, the frequency is fixed, assume VO and η are constants, we can get





(







) ………(14)

NL Mode Operation

At no load and ultra light load, the AP3984 works at no load mode (NL mode) and the output voltage is detected by AP4341. In order to achieve

ultra low standby power at NL mode, the static current (ICC_NL) of the AP3984 is reduced to 17.5μA.

• The conditions of exiting NL mode---VCPC>60mV or tOFF<256μs

• The conditions of entering NL mode-- VCPC<60mV and tOFF≥256μs

At NL mode, the internal reference voltage VDD is pulled to ground. For normal NL working state, there are two mechanisms that make the

AP3984 re-establish the VDD, then generate the PFM pulse to turn on primary switch. One is when the AP4341 detects the output voltage is lower

than its trigger voltage. The AP4341 OUT pin emits a periodical pulse current. This pulse current will generate a pulse voltage on feedback

winding through the transformer coupling. When the FB pin of AP3984 detects this pulse (>75mV is valid), the AP3984 re-establishes the VDD and

turns on primary switch to provide one energy pulse to supply output terminal and primary VCC voltage. The other is when VCC voltage of the

AP3984 lower than LVCC voltage (about 7.5V). To achieve low standby power, the lower switching frequency is necessary. But if the off time is

too long, the VCC voltage will reduce to very low level. This mechanism is better to avoid VCC voltage being lower than VOPR(MIN).

Leading Edge Blanking

When the power switch is turned on, a turn-on spike will occur on the sense-resistor. To avoid false-termination of the switching pulse, a 500ns

leading-edge blanking is built in. During this blanking period,

the current sense comparator is disabled and the driver can’t be switched off.

Valley Turn-on

When the off time (tOFF) is lower than tVAL-ON, AP3984 power system can work with valley turn-on. It can reduce BJT switching on power losses

which is resulted from the equivalent output capacitance to achieve highest overall efficiency. At the same time, because of valley turn-on the

switching frequency has the random jitter feature, which will benefit for conductive EMI performance. And valley turn-on can also reduce the

power switch turn on spike current and then achieve the better radiative EMI performance.

Adjustable Line Compensation

Since there is a constant delay time from the CS pin voltage reaching the given VCS reference to the power BJT turning off, the real primary peak

current value always has a gap with the ideal value. The gap value changes with different input line voltage, which is caused by different current

rising slope, results in different system constant current value.

In order to eliminate the constant current deviation due to line voltage, the adjustable line compensation is introduced to AP3984 design. The

negative voltage of FB pin which is linear to the line voltage is added up to VCS reference by a certain proportion and create an adjustable

compensation voltage to clear up the primary current gap, so that the excellent line regulation of output current will be achieved.

RFB1

RFB2

PFM

VAUX

VSAMPLE

VCS

RLC

Figure 6. Adjustable Line Compensation Circuit

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