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DA9313

High Efficiency Dual Cell Switched Capacitor Divider

Datasheet

Revision 3.0

07-Apr-2017

CFR0011-120-00

32 of 54

Control bit

Block

PVC_DIS_SL

PVC enable control, in SLEEP mode:

0: no change

1: PVC disabled

The PVC is disabled

PVC_EN setting is overwritten (old value restored at the exit of SLEEP mode)

VDDIO_DIS_SL

Control VDDIO supply enable, in SLEEP mode:

0: no change

1: VDDIO rail disabled. IOs supplied from VCORE

11.5 FAULT RECOVERY Mode

DA9313 responds to critical under-voltage, over-current, and over-temperature conditions and safely

power cycles the device through FAULT RECOVERY mode. Fault events are captured in the

FAULT_LOG register for host interrogation on reboot and warning levels generate maskable interrupt

events.

FAULT RECOVERY is a temporary mode and is automatically entered and exited depending on fault

condition presence. DA9313 enters FAULT RECOVERY mode from ACTIVE or SLEEP mode. In

POWER_DOWN mode there is no supervision therefore FAULT RECOVERY mode cannot be

entered.

The device waits for a configurable FAULT_TIME, when the PVC is disabled, to ensure discharge of

all critical nodes in the application before any attempt to reboot. DA9313 automatically exits FAULT

RECOVERY mode when the fault condition has expired.

The FAULT_LOG register can be reset by a register write of 1 to the appropriate register bit.

11.5.1

Input Under-Voltage

VBAT voltage is continuously sensed, except in RESET and POWER_DOWN modes, by dedicated

analog circuitry based on two configurable levels: a warning level, VTH_WARN and a shutdown level,

VTH_UVLO_VDD.

The upper comparator triggers a warning if VBAT drops below VTH_WARN. The lower comparator

triggers a fault condition if VBAT drops below VTH_UVLO_VDD.

The VTH_UVLO_VDD voltage threshold is configurable and can be set via VBAT_UV_CRIT_THRSH from

4.6 V to 6.15 V (5.0 V default) in steps of 50 mV.

The VHYST_UVLO_VDD hysteresis can be also be configured via VBAT_UV_HYS from 50 mV to 400 mV

(200 mV default) in steps of 50 mV.

The VTH_WARN voltage threshold is configurable and can be set via VBAT_UV_WARN from 5.2 V to

6.6 V in steps of 200 mV.

To reduce the current consumption of the block only the warning comparator is permanently on, the

shutdown comparator is enabled on demand in the interval where VBAT is below the warning

threshold.

The critical under voltage threshold comparator is also debounced, this guarantees that short spikes

do not trigger the application power-down.

When the warning comparator triggers, the status bit VBAT_WARN is asserted and the event

E_VBAT_WARN is generated. If not masked via M_VBAT_WARN, the output port nIRQ is asserted

(providing a GPIO is configured as nIRQ). The host processor is then informed that the input voltage

level is close to critical and it can take action such as powering down the application.

If the input voltage keeps dropping and the shutdown comparator is triggered the PVC is disabled

and the VBAT_UV_CRIT bit is asserted in FAULT_LOG. When the VBAT voltage recovers over

VTH_UVLO_VDD + VHYST_UVLO_VDD, DA9313 enters ACTIVE mode after having performed an OTP read.

DA9313 Datasheet(PDF) 32 Page - Dialog Semiconductor

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