SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

t

(BUF)

S

S

P

P

6

INA231

SBOS644B – FEBRUARY 2013 – REVISED AUGUST 2017

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(1)

Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are specified by design, but not

production tested.

7.6 Timing Requirements: I

FAST MODE

HIGH-SPEED MODE

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

0.001

0.4

0.001

2.5

MHz

Bus free time between stop

and start conditions

600

260

ns

Hold time after repeated

START condition.

After this period, the first clock

is generated.

100

100

ns

Repeated start condition setup

time

100

100

ns

100

100

ns

0

0

130

ns

10

10

130

ns

100

50

ns

1300

260

ns

600

60

ns

300

80

ns

300

80

ns

300

40

ns

300

40

ns

Clock/data rise time for SCLK

≤ 100 kHz

1000

ns

Figure 1. Bus Timing Diagram