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LP87322B/D Datasheet(PDF) 53 Page - Texas Instruments |
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LP87322B/D Datasheet(HTML) 53 Page - Texas Instruments |
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53 / 75 page  53 LP87322B-Q1, LP87322D-Q1, LP87322E-Q1, LP87322F-Q1 www.ti.com SNVSAC5 – SEPTEMBER 2017 Product Folder Links: LP87322B-Q1 LP87322D-Q1 LP87322E-Q1 LP87322F-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Bits Field Type Default Description 4 SYNC_CLK _MASK R/W 1 * Masking for external clock detection interrupt (SYNC_CLK_INT in INT_TOP_1 register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect SYNC_CLK_STAT status bit in TOP_STAT register. 3 Reserved R/W 0 2 TDIE_WARN _MASK R/W 0 * Masking for thermal warning interrupt (TDIE_WARN_INT in INT_TOP_1 register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect TDIE_WARN_STAT status bit in TOP_STAT register. 1 Reserved R/W 0 0 I_MEAS _MASK R/W 0 * Masking for load current measurement ready interrupt (MEAS_INT in INT_TOP_1 register). 0 - Interrupt generated 1 - Interrupt not generated. 8.6.1.34 TOP_MASK_2 Address: 0x21 D7 D6 D5 D4 D3 D2 D1 D0 Reserved RESET_REG _MASK Bits Field Type Default Description 7:1 Reserved R/W 000 0000 0 RESET_REG _MASK R/W 1 * Masking for register reset interrupt (RESET_REG_INT in INT_TOP_2 register): 0 - Interrupt generated 1 - Interrupt not generated. This change of this bit by I2C writing has no effect because it will be read from OTP memory during reset. 8.6.1.35 BUCK_MASK Address: 0x22 D7 D6 D5 D4 D3 D2 D1 D0 BUCK1_PGF _MASK BUCK1_PGR _MASK Reserved BUCK1_ILIM _MASK BUCK0_PGF _MASK BUCK0_PGR _MASK Reserved BUCK0_ILIM _MASK Bits Field Type Default Description 7 BUCK1_PGF_MAS K R/W 1 * Masking of Power Good invalid detection for Buck1 power good interrupt (BUCK1_PG_INT in INT_BUCK register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK1_PG_STAT status bit in BUCK_STAT register. 6 BUCK1_PGR_MAS K R/W 1 * Masking of Power Good valid detection for Buck1 Power Good interrupt (BUCK1_PG_INT in INT_BUCK register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK1_PG_STAT status bit in BUCK_STAT register. 5 Reserved R 0 4 BUCK1_ILIM _MASK R/W 0 * Masking for Buck1 current limit detection interrupt (BUCK1_ILIM_INT in INT_BUCK register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK1_ILIM_STAT status bit in BUCK_STAT register. 3 BUCK0_PGF_MAS K R/W 1 * Masking of Power Good invalid detection for Buck0 power good interrupt (BUCK0_PG_INT in INT_BUCK register): 0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK0_PG_STAT status bit in BUCK_STAT register. |
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