XR68C92IP datasheet(6/32 Pages) EXAR

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XR68C92/192

Rev. P1.10

SYMBOL DESCRIPTION (* 44 TQFP Package)

Symbol

Signal

Pin Description

44*

type

active low).

IP2

Multi-purpose input or Timer/Counter External clock input.

IP3

Multi-purpose input or Channel A transmit external clock

input. The transmit data is clocked on the falling edge of the

clock.

IP4

Multi-purpose input or Channel A receive external clock

input. The received data is clocked on the rising edge of the

clock.

IP5

Multi-purpose input or Channel B Transmit external clock

input. The transmit data is clocked on the falling edge of the

clock.

-IACK

Interrupt acknowledge (active low). Indicating an interrupt

acknowledge cycle. XR68C92/192 will place the interrupt

vector on the data bus and will set -DTACK low if it has a

pending interrupt.

-CS

Chip select (active low). A low at this pin enables the serial

port / CPU data transfer operation.

D0-D7

28,18

25,16

22,12

Bi-directional data bus. Eight bit, three state data bus to

27,19

24,17

21,13

I/O

transfer information to or from the CPU. D0 is the least

26,20

23,18

20,14

significant bit of the data bus and the first serial data bit to be

25,21

22,19

19,15

received or transmitted.

R/-W

Read/Write strobe. When -CS is asserted, a high level on this

pin transfers the contents of the XR68C92/192 data bus to

the CPU, and a low level on this pin will transfer the contents

of the CPU data bus to the addressed register.

VCC

38,39

Pwr

Power supply input.

N.C.

1,12

11,23

No Connection.

23,34

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