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74HCT164BQ Datasheet(PDF) 13 Page - NXP Semiconductors |
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74HCT164BQ Datasheet(HTML) 13 Page - NXP Semiconductors |
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13 / 24 page  9397 750 14693 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 4 April 2005 13 of 24 Philips Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register Table 10: Dynamic characteristics for 74HCT164 GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Tamb = 25 °C tPHL, tPLH propagation delay CP to Qn VCC = 4.5 V; see Figure 7 - 1736ns tPHL propagation delay MR to Qn VCC = 4.5 V; see Figure 8 - 1938ns tTHL, tTLH output transition time VCC = 4.5 V; see Figure 7 - 7 15 ns tW clock pulse width; HIGH or LOW VCC = 4.5 V; see Figure 7 18 7 - ns master reset pulse width; LOW VCC = 4.5 V; see Figure 8 18 10 - ns trem removal time MR to CP VCC = 4.5 V; see Figure 8 16 7 - ns tsu set-up time DSA, and DSB to CP VCC = 4.5 V; see Figure 9 12 6 - ns th hold time DSA, and DSB to CP VCC = 4.5 V; see Figure 9 +4 −2- ns fmax maximum clock pulse frequency VCC = 4.5 V; see Figure 7 27 55 - MHz Tamb = −40 °C to +85 °C tPHL, tPLH propagation delay CP to Qn VCC = 4.5 V; see Figure 7 --45 ns tPHL propagation delay MR to Qn VCC = 4.5 V; see Figure 8 --48 ns tTHL, tTLH output transition time VCC = 4.5 V; see Figure 7 --19 ns tW clock pulse width; HIGH or LOW VCC = 4.5 V; see Figure 7 23 --ns master reset pulse width; LOW VCC = 4.5 V; see Figure 8 23 --ns trem removal time MR to CP VCC = 4.5 V; see Figure 8 20 --ns tsu set-up time DSA, and DSB to CP VCC = 4.5 V; see Figure 9 15 --ns th hold time DSA, and DSB to CP VCC = 4.5 V; see Figure 9 4 --ns fmax maximum clock pulse frequency VCC = 4.5 V; see Figure 7 22 - - MHz Tamb = −40 °C to +125 °C tPHL, tPLH propagation delay CP to Qn VCC = 4.5 V; see Figure 7 --54 ns tPHL propagation delay MR to Qn VCC = 4.5 V; see Figure 8 --57 ns tTHL, tTLH output transition time VCC = 4.5 V; see Figure 7 --22 ns |
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