CY28329

..................... Document #: 38-07040 Rev. *E Page 11 of 16

VDD and POR Timing

3V66

PCI

3V66-PCI Clock Skew

CPU Clock Cycle-Cycle Jitter

Host_b

Host

Cycle-Cycle Clock Jitter

CLK

POR

1.5V

VDD

1.5V

t

10