SL28610

........................ DOC #: SP-AP-0078 (Rev. 1.0) Page 3 of 23

Frequency Select Pin (FSB and FSC)

Apply the appropriate logic levels to FSB and FSC inputs

before CKPWRGD assertion to achieve host clock frequency

selection. When the clock chip sampled LOW on CKPWRGD

and indicates that VTT voltage is stable then FSB and FSC

input values are sampled. This process employs a one-shot

functionality and once the CKPWRGD sampled a valid LOW,

all other FSB, FSC, and CKPWRGD transitions are ignored

except in test mode.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers are individually enabled or disabled. The

registers associated with the Serial Data Interface initialize to

their default setting at power-up. The use of this interface is

optional. Clock device register changes are normally made at

system initialization, if any are required. The interface cannot

be used during system operation for power management

functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, access the bytes in sequential

order from lowest to highest (most significant bit first) with the

ability to stop after any complete byte is transferred. For byte

write and byte read operations, the system controller can

access individually indexed bytes. The offset of the indexed

byte is encoded in the command code described in Table 2.

The block write and block read protocol is outlined in Table 3

while Table 4 outlines byte write and byte read protocol. The

slave receiver address is 11010010 (D2h).

.

40

VSS

GND

Ground

41

VDD1.5_IO

PWR

1.5V Power Supply for differential output

42

VDD1.5_CORE

PWR

1.5V Power Supply for core

43

CPU1#

O, DIF Complementary Host Differential clock

44

CPU1

O, DIF True Host Differential clock

45

VSS_CPU

GND

Ground

46

VDD1.5_IO

PWR

1.5V Power Supply for differential output

47

CPU2#

O, DIF Complementary Host Differential clock

48

CPU2

O, DIF True Host Differential clock

Table 1. Frequency Select Pin (FSB and FSC)

FSC

FSB

CPU

PCIe

LCD

DOT96

REF

1

0

100 MHz

100 MHz

100 MHz

96 MHz

14.318 MHz

0

0

133 MHz

100 MHz

100 MHz

96 MHz

14.318 MHz

0

1

166 MHz

100 MHz

100 MHz

96 MHz

14.318 MHz

1

1

200 MHz

100 MHz

100 MHz

96 MHz

14.318 MHz

Pin No.

Name

Type

Description

Table 2. Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'

Table 3. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

1Start

1

Start

8:2

Slave address–7 bits

8:2

Slave address–7 bits

9

Write

9

Write

10

Acknowledge from slave

10

Acknowledge from slave

18:11

Command Code–8 bits

18:11

Command Code–8 bits

19

Acknowledge from slave

19

Acknowledge from slave