W311

....................... Document #: 38-07703 Rev. ** Page 13 of 18

How to Program CPU Output Frequency

When the programmable output frequency feature is enabled

(Pro_Freq_EN bit is set), the CPU output frequency is deter-

mined by the following equation:

Fcpu = G * (N+3)/(M+3)

“N” and “M” are the values programmed in Programmable

Frequency Select N-Value Register and M-Value Register,

respectively.

“G” stands for the PLL Gear Constant, which is determined by

the programmed value of FS[4:0] or SEL[4:0]. The value is

listed in Table 5. The ratio of (N+3) and (M+3) need to be

greater than “1” [(N+3)/(M+3) > 1].

Table 7 lists set of N and M values for different frequency

output ranges.This example use a fixed value for the M-Value

Register and select the CPU output frequency by changing the

value of the N-Value Register.

FS_Override

When Pro_Freq_EN is cleared or disabled,

0 = Select operating frequency by FS input pins (default)

1 = Select operating frequency by SEL bits in SMBus control bytes

When Pro_Freq_EN is set or enabled,

0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are

based on the latched value of FS input pins (default)

1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are

based on the programmed value of SEL bits in SMBus control bytes

CPU_FSEL_N,

CPU_FSEL_M

ROCV_FREQ_SEL

When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and CPU_F-

SEL_M[6:0] determines the CPU output frequency. The new frequency will start to load whenever there

is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recommended to use

Word or Block write to update both registers within the same SMBus bus operation.

The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PCI. When

FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins.

When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in

SMBus control bytes.

ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer timeout

occurs. The clock generator will automatically switch to the recovery CPU frequency based on the

selection on ROCV_FREQ_SEL.

0 = From latched FS[4:0]

1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]

WD_PRE_SCALER

0 = 150 ms

1 = 2.5 sec

RST_EN_WD

This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs.

0 = Disabled

1 = Enabled

RST_EN_FC

This bit will enable the generation of a Reset pulse after a frequency change occurs.

0 = Disabled

1 = Enabled

Table 6. Register Summary (continued)

Name

Description

Table 7. Examples of N and M Value for Different CPU Frequency Range

Frequency Ranges

Gear Constants

Fixed Value for

M-Value Register

Range of N-Value Register

for Different CPU Frequency

50 MHz–129 MHz

48.00741

93

97–255

130 MHz–248 MHz

48.00741

45

127–245