Document Number: 002-08228 Rev. *C

Page 13 of 41

MB39C007

(Ta

= +25°C, AVDD = DVDD1 = DVDD2 = 3.7 V, VOUT1/VOUT2 setting value = 2.5 V, MODE1/MODE2 = 0 V)

[3] : The + leak at the LX1 pin and LX2 pin includes the current of the internal circuit.

[4] : Sum of the current flowing into the AVDD, the DVDD1, and the DVDD2 pins.

[5] : Current consumption based on 100% ON-duty (High side FET in full ON state). The SW FET gate drive current is not

included because the device is in full ON state (no switching operation). Also the load current is not included.

Parameter

Symbol

Pin No.

Condition

Value

Unit

Min

Typ

Max

Control block

CTL threshold voltage

1, 2, 3

-

0.55

0.95

1.45

V

-

0.40

0.80

1.30

V

CTL pin

input current

0 V

≤ CTLP/CTL1/CTL2 ≤ 3.7 V

--

1.0

μA

Reference

voltage block

VREF voltage

6

VREF

= 0 A

1.274

1.300

1.326

V

VREF Load stability

VREF

= −1.0 mA

--

20

mV

General

Shut down power supply

current

5, 11,

12, 19,

20

CTLP/CTL1/CTL2

= 0 V,

--

1.0

μA

CTLP/CTL1/CTL2

V,

--

1.0

μA

Power supply current at

DC/DC operation 1

(PFM mode)

1. CTLP

= 0 V,CTL1 = 3.7 V,

CTL2

= 0 V

2. CTLP

= 0 V, CTL1 = 0 V,

CTL2

= 3.7 V, OUT = 0 A

-

30

48

μA

CTLP

= 0 V, CTL1/CTL2 = 3.7 V,

OUT

= 0 A

-

50

80

μA

Power supply current at

DC/DC operation 2

(PWM mode)

1. CTLP

= 0 V, CTL1 = 3.7 V,

CTL2

= 0 V, MODE1/

MODE2

= OPEN

2. CTLP

= 0 V, CTL1 = 0 V,

CTL2

= 3.7 V, MODE1/

MODE2

= OPEN,

OUT

= 0 A

-

3.5

10.0

mA

CTLP

= 0 V, CTL1/CTL2 = 3.7 V,

MODE1/MODE2

= OPEN, OUT = 0

A

-

7.0

20.0

mA

Power supply current

(voltage detection mode)

CTLP

= 3.7 V,

CTL1/CTL2

= 0 V

-

15

24

μA

Power-on invalid current

1. CTL1

= 3.7 V, CTL2 = 0 V

2. CTL1

= 0 V, CTL2 = 3.7 V,

VOUT1/VOUT2

= 90%,

OUT

-

1000

2000

μA