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ADC10064CIWM Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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ADC10064CIWM Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 14 page  Pin Descriptions DV CC,AVCC These are the digital and analog positive sup- ply voltage inputs. They should always be connected to the same voltage source, but are brought out separately to allow for sepa- rate bypass capacitors. Each supply pin should be bypassed with a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor to ground. INT This is the active low interrupt output. INT goes low at the end of each conversion, and returns to a high state following the rising edge of RD. S/H This is the Sample/Hold control input. When this pin is forced low (and CS is low), it causes the analog input signal to be sampled and initiates a new conversion. RD This is the active low Read control input. When this RD and CS are low, any data present in the output registers will be placed on the data bus. CS This is the active low Chip Select control in- put. When low, this pin enables the RD and S/H pins. S0, S1 On the multiple-input devices (ADC10062 and ADC10064), these pins select the analog input that will be connected to the A/D during the conversion. The input is selected based on the state of S0 and S1 when S/H makes its High-to-Low transition (See the Timing Dia- grams). The ADC10064 includes both S0 and S1. The ADC10062 includes just S0, and the ADC10061 includes neither. V REF−,VREF+ These are the reference voltage inputs. They may be placed at any voltage between GND and V CC, but VREF+ must be greater than V REF−. An input voltage equal to VREF− pro- duces an output code of 0, and an input volt- age equal to (V REF+ − 1 LSB) produces an output code of 1023. V IN,VIN0,VIN1,VIN2, V IN3 These are the analog input pins. The ADC10061 has one input (V IN), the ADC10062 has two inputs (V IN0 and VIN1), and the ADC10064 has four inputs (V IN0, V IN1,VIN2 and VIN3). The impedance of the source should be less than 500 Ω for best accuracy and conversion speed. For accurate conversions, no input pin (even one that is not selected) should be driven more than 50 mV above V CC or 50 mV below ground. GND, AGND, DGND These are the power supply ground pins. The ADC10061 has a single ground pin (GND), and the ADC10062 and ADC10064 have separate analog and digital ground pins (AGND and DGND) for separate bypassing of the analog and digital supplies. The ground pins should be connected to a stable, noise-free system ground. For the devices with two ground pins, both pins should be returned to the same potential. DB0–DB9 These are the TRI-STATE® output pins. SPEED ADJ (ADC10062 and ADC10064 only). This pin is normally left unconnected, but by connecting a resistor between this pin and ground, the conversion time can be reduced. See the Typical Performance Curves and the table of Electrical Characteristics. www.national.com 3 |
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