PRELIMINARY

CY2XP21

125 MHz LVPECL Clock Generator

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document #: 001-52849 Rev. *B

Revised September 22, 2009

Features

(1.875 MHz to 20 MHz): 0.4 ps (Typical)

Functional Description

The CY2XP21 is a PLL (Phase Locked Loop) based high

performance clock generator. It is optimized to generate a

125 MHz clock, which is ideal for 10 Gb Ethernet applications. It

also produces an output frequency that is five times the crystal

frequency. It uses Cypress’s low noise VCO technology to

achieve less than 1 ps typical RMS phase jitter. The CY2XP21

has a crystal oscillator interface input and one LVPECL output

pair.

OUTPU T

DIVIDER

CR YSTAL

OSCILLATOR

CLK#

LOW -N OISE

PLL

CLK

XOU T

XIN

External

Crystal

Logic Block Diagram

Pinouts

Figure 1. Pin Diagram - 8-Pin TSSOP

1

2

36

7

8

XOUT

XIN

NC

VSS

VDD

CLK#

45

VDD

CLK

Table 1. Pin Definition - 8-Pin TSSOP

Pin Number

Pin Name

I/O Type

Description

1, 8

VDD

Power

3.3V or 2.5V power supply

2

VSS

Power

Ground

3, 4

XOUT, XIN

XTAL output and input

Parallel resonant crystal interface

5

NC

No Connect

6,7

CLK#, CLK

LVPECL output

Differential clock output

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