CY7C1663KV18 datasheet(16/31 Pages) CYPRESS

Part #	CY7C1663KV18

Description	144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

PDF	31 Pages

Scroll/Zoom	100%

Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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16 / 31 page

Document Number: 001-44060 Rev. *O

Page 16 of 31

CY7C1663KV18/CY7C1665KV18

TAP AC Switching Characteristics

Over the Operating Range

Parameter [19, 20]

Description

Min

Max

Unit

tTCYC

TCK clock cycle time

–

tTF

TCK clock frequency

–

MHz

tTH

TCK clock high

–

tTL

TCK clock low

–

Setup Times

tTMSS

TMS setup to TCK clock rise

–

tTDIS

TDI setup to TCK clock rise

–

tCS

Capture setup to TCK rise

–

Hold Times

tTMSH

TMS hold after TCK clock rise

–

tTDIH

TDI hold after clock rise

–

tCH

Capture hold after clock rise

–

Output Times

tTDOV

TCK clock low to TDO valid

–

tTDOX

TCK clock low to TDO invalid

–

Notes

19. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

20. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

CY7C1663KV18 Datasheet(PDF) 16 Page - Cypress Semiconductor

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