Kawasaki USB device

KL5KUSB201

Copyright © 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.

HS_SIE IP is useful for Kawasaki ASIC users to design their LSI, which connects to

KL5KUSB201 or includes USB201 IP inside. Together with KL5KUSB201 chip, the IP

performs USB2.0 lower level protocol. The main features of HS_SIE are shown below.

1. RTL design makes it easy to implement with various processes

2. Compact design such as 20 k logic gates, 4x512 bytes and 1x64 bytes 1-p RAM

3. Performs HS chirp protocol and Speed detection

4. Processes the basic USB transaction such as token decode, miss-hit judgment,

error detection and data toggle bit control

5. Controls transaction flow

6. Supports up to 6 endpoints in total – control, 2 bulk in, 2 bulk out and interrupt.

7. Ease-of-use internal bus interface such as 16bit bus register access or DMA

Figure 9-4-1 HS_SIE IP Symbol

HS_SIE

SIE bus

IHOST bus

CKOUT

FS_HSN

RXACT

RXVLD

WDVLD

PU_SE0N

SIE_DAT[15:0]

RXERR

CRCERR

TXACT

TXRDY

CRCACT

BSTAT[1:0]

SUSPN

URSTN

MODE[3:0]

HCSN

HIRQ

HWRN

HRDY

HDAT[15:0]

HREQ

SYSCK

HRDN

HADR[4:0]

HACK

RXLBVLD

RXLAST

TXLBVLD

TXLAST

RSTN

TXNUL