SMP9410F datasheet(9/13 Pages) ETC

9 / 13 page

SMP9410

SUMMIT MICROELECTRONICS, Inc.

Preliminary Information

2056 2.0 10/04/02

Master

SDA

Slave

1 0 0 1

Optional

2056 Fig05

Configuration Data Byte

Master

SDA

Slave

0 1 0 1

2056 Fig04

DAC

x x x x

1 0 0 1

Data from Master

Data to Master

x x x x x x

Master

SDA

Slave

0 1 0 1

1 0 0 1

Nonvolatile Write Only

2056 Fig03

Command Data Byte

ACK and NACK

A device that is receiving data will respond with an Acknowl-

edge by pulling the SDA line low (ACK) after each byte is

transmitted. The transmitting device will recognize this and

continue to transmit. When the Master has received the

data it expects it will hold the SDA line high (NACK) and the

transmitting device will end transmission.

Sequence

The sequence is to issue a Start, followed by the device

type and bus address with the Read/Write bit set to zero.

The device will respond with an Acknowledge and the

Master will then issue the command and follow-on data. In

Figure 5 the Write is to DAC1 where the command =

1001BIN; D9 and D8 are the MSBs of the DAC value being

written. The device will then respond with an Acknowledge

followed by the Master writing the last eight bits. If no Stop

is generated after the device Acknowledge the Write is only

to the register. If the device Acknowledge is followed by a

Stop the data is written to both the DAC register and to the

nonvolatile register.

Reading the Device

Reading the DACs requires setting the R/W bit to one. Then

the host supplies clocks and the device will output data as

shown in Figure 6.

Configuration Register

The SMP9410 can be configured by the end user or by

Summit prior to shipment (see Programming Information).

Reading the configuration register can also be performed if

it has not already been locked. See Figure 7. There is one

configuration register and it is accessed through the serial

interface using 1001BIN as the device type address, conse-

quently the DAC address should never be set to 1001BIN.

The register is shown in Table 3.

Figure 5. DAC1 Write Operation (see Table 2)

Figure 6. Read DACs

APPLICATIONS INFORMATION (CONTINUED)

Figure 7. Configuration Register (see Table 3)

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