SIC769CD datasheet(8/18 Pages) VISHAY

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Document Number: 64981

S11-0975-Rev. F, 16-May-11

Vishay Siliconix

SiC769

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

PIN CONFIGURATION

Figure 5 - PowerPAK MLP 6 x 6 40P Pin Out - Top View

VIN

AGND

VSWH

30 VSWH

29 VSWH

28 PGND

27 PGND

26 PGND

25 PGND

24 PGND

23 PGND

22 PGND

21 PGND

SMOD 1

VCIN 2

VDRV 3

BOOT 4

CGND 5

GH 6

PHASE 7

VIN 8

VIN 9

VIN 10

PIN DESCRIPTION

Pin Number

Symbol

Description

SMOD

Disable low side gate operation. Active low.

2VCIN

This will be the bias supply input for control IC (5 V).

3VDRV

IC bias supply and gate drive supply voltage (5 V).

BOOT

High side driver bootstrap voltage pin for external bootstrap capacitor.

5, 37, PAD1

CGND

Control signal ground. It should be connected to PGND externally. All pins internally connected.

Gate signal output pin for high side MOSFET. Pin for monitoring.

PHASE

Return pin for the HS bootstrap capacitor. Connect a 0.1 µF ceramic capacitor from this pin to the boot pin (4).

8 to 14, PAD2

VIN

Input voltage for power stage. It is the drain of the high-side MOSFET.

15, 29 to 35,

PAD3

VSWH

It is the phase node between high side MOSFET source and low side MOSFET drain. It should be connected

to an output inductor. All pins internally connected.

16 to 28

PGND

Power ground.

Gate signal output pin for low side MOSFET. Pin for monitoring.

THDN

Thermal shutdown open drain output. Use a 10K pull up resistor to VCIN.

DSBL#

Disable pin. Active low.

PWM

PWM input logic signal. Compatible with Tristate controller function.

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