UT9Q512K32 datasheet(2/14 Pages) AEROFLEX

2 / 14 page

PIN NAMES

DEVICE OPERATION

The UT9Q512 has three control inputs called Enable 1 (En),

Write Enable (Wn), and Output Enable (G); 19 address inputs,

A(18:0); and eight bidirectional data lines, DQ(7:0). En Device

Enable controls device selection, active, and standby modes.

Asserting En enables the device, causes IDD to rise to its active

value, and decodes the 19 address inputs to select one of 524,288

words in the memory. Wn controls read and write operations.

During a read cycle, G must be asserted to enable the outputs.

Table 1. Device Operation Truth Table

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

READ CYCLE

A combination of Wn greater than V

IH (min) and En less than

VIL (max) defines a read cycle. Read access time is measured

from the latter ofDeviceEnable, Output Enable, or valid address

to valid data output.

SRAM Read Cycle 1, the Address Access in figure 3a, is

initiated by a change in address inputs while the chip is enabled

with G asserted and Wn deasserted. Valid data appears on data

outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs

remain active throughout the entire cycle. As long as Device

Enable and Output Enable are active, the address inputs may

change at a rate equal to the minimum read cycle time (t

AVAV).

SRAM read Cycle 2, the Chip Enable - Controlled Access in

figure 3b, is initiated by En going active while G remains

asserted, Wn remains deasserted, and the addresses remain

stable for the entire cycle. After the specified tETQV is satisfied,

the eight-bit word addressed by A(18:0) is accessed and appears

at the data outputs DQ(7:0).

SRAM read Cycle 3, the Output Enable - Controlled Access in

figure 3c, is initiated byG going active while En is asserted, Wn

is deasserted, and the addresses are stable. Read access time is

tGLQV unless tAVQV or tETQV have not been satisfied.

A(18:0)

Address

Write Enable

DQn(7:0)

Data Input/Output

Output Enable

Enable

VDD Power

VSS

Ground

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Top View

DQ0(0)

DQ1(0)

DQ2(0)

DQ3(0)

DQ4(0)

DQ5(0)

DQ6(0)

DQ7(0)

VSS

DQ0(1)

DQ1(1)

DQ2(1)

DQ3(1)

DQ4(1)

DQ5(1)

DQ6(1)

DQ7(1)

DQ0(2)

DQ1(2)

DQ2(2)

DQ3(2)

DQ4(2)

DQ5(2)

DQ6(2)

DQ7(2)

VSS

DQ0(3)

DQ1(3)

DQ2(3)

DQ3(3)

DQ4(3)

DQ5(3)

DQ6(3)

DQ7(3)

Figure 2. 25ns SRAM Pinout (68)

I/O Mode

Mode

3-state

Standby

Data in

Write

3-state

Data out

Read

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