CS5345

22

4.2.2

Master Mode

As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from MCLK with

LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 8.

4.2.3

Slave Mode

In Slave mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sample rate,

Fs, and must be synchronously derived from the supplied master clock, MCLK.

The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to 128x, 64x,

48x or 32x Fs depending on the desired speed mode. Refer to Table 3 for required clock ratios.

4.3

High Pass Filter and DC Offset Calibration

When using operational amplifiers in the input circuitry driving the CS5345, a small DC offset may be driven into the

A/D converter. The CS5345 includes a high pass filter after the decimator to remove any DC offset which could result

in recording a DC level, possibly yielding clicks when switching between devices in a multichannel system.

LRCK

(kHz)

MCLK (MHz)

64x

96x

128x

192x

256x

384x

512x

768x

1024x

32

-

---

8.1920

12.2880

16.3840

24.5760

32.7680

44.1

-

---

11.2896

16.9344

22.5792

33.8680

45.1584

48

-

---

12.2880

18.4320

24.5760

36.8640

49.1520

64

-

-

8.1920

12.2880

16.3840

24.5760

32.7680

-

-

88.2

-

-

11.2896

16.9344

22.5792

33.8680

45.1584

-

-

96

-

-

12.2880

18.4320

24.5760

36.8640

49.1520

-

-

128

8.1920

12.2880

16.3840

24.5760

32.7680

-

-

-

-

176.4

11.2896

16.9344

22.5792

33.8680

45.1584

-

-

-

-

192

12.2880

18.4320

24.5760

36.8640

49.1520

-

-

-

-

Mode

QSM

DSM

SSM

Table 2. Common Clock Frequencies

Single Speed

Double Speed

Quad Speed

SCLK/LRCK Ratio

32x, 48x, 64x, 128x

32x, 48x, 64x

32x, 48x, 64x

Table 3. Slave Mode Serial Bit Clock Ratios

÷256

÷128

÷64

÷4

÷2

÷1

00

01

10

00

01

10

LR C K

SC LK

000

001

010

÷1

÷1.5

÷2

011

100

÷3

÷4

MC LK

FM Bits

MC LK F re q Bits

Figure 8. Master Mode Clocking