DS2153Q datasheet(5/52 Pages) DALLAS

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DS2153Q

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PIN DESCRIPTION Table 1-1

SYMBOL

TYPE

DESCRIPTION

AD4

AD5

AD6

AD7

I/O

Address/Data Bus. An 8-bit multiplexed address/data bus.

(DS)

Read Input (Data Strobe).

Chip Select. Must be low to read or write the port.

7ALE(AS)

Address Latch Enable (Address Strobe). A positive going edge

serves to demultiplex the bus.

(R/ W )

Write Input (Read/Write).

9RLINK

Receive Link Data. Outputs the full receive data stream including

the Sa bits. See Section 13 for timing details.

RLCLK

Receive Link Clock. 4 kHz to 20 kHz demand clock for the RLINK

output; controlled by RCR2. See Section 13 for timing details.

DVSS

Digital Signal Ground. 0.0 volts. Should be tied to local ground

plane.

RCLK

Receive Clock. Recovered 2.048 MHz clock.

RCHCLK

Receive Channel Clock. 256 kHz clock which pulses high during

the LSB of each channel. Useful for parallel to serial conversion of

channel data. See Section 13 for timing details.

RSER

Receive Serial Data. Received NRZ serial data, updated on rising

edges of RCLK or SYSCLK.

RSYNC

I/O

Receive Sync. An extracted pulse, one RCLK wide, is output at this

pin which identifies either frame (RCR1.6=0) or multiframe

boundaries (RCR1.6=1). If the elastic store is enabled via the

RCR2.1, then this pin can be enabled to be an input via RCR1.5 at

which a frame boundary pulse is applied. See Section 13 for timing

details.

RLOS/LOTC

Receive Loss of Sync/Loss of Transmit Clock. A dual function

output. If TCR2.0=0, will toggle high when the synchronizer is

searching for the E1 frame and multiframe; if TCR2.0=1, will toggle

high if the TCLK pin has not toggled for 5

µs.

SYSCLK

System Clock. 1.544 MHz or 2.048 MHz clock. Only used when

the elastic store functions are enabled via RCR2.1. Should be tied

low in applications that do not use the elastic store. If tied high for at

least 100

µs, will force all output pins (including the parallel port) to

3-state.

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