THE DEMODULATOR SECTION

The Receive Filter

The demodulator recovers the data from the received sig-

nals The signal from the hybrid is a mixture of transmitted

signal received signals and noise The first stage of the

receive filter is an anti-alias filter which attenuates high fre-

quency noise before sampling occurs The signal then goes

to the second stage of the receive filter where the transmit-

ted tones and other noise are filtered from the received sig-

nal This is a switch capacitor nine pole filter providing at

least 60 dB of transmitted tone rejection This also provides

high attenuation at 60Hz a common noise component

The Discriminator

The first stage of the discriminator is a hard limiter The hard

limiter removes from the received signal any amplitude

modulation which may bias the demodulator toward a mark

or a space It compares the output of the receive filter to the

voltage on the 01 mF capacitor on the FTLC pin

The hard limiter output connects to two parallel bandpass

filters in the discriminator One filter is tuned to the mark

frequency and the other to the space frequency The out-

puts of these filters are rectified filtered and compared If

the output of the mark path exceeds the output of the space

path the RXD output goes high The opposite case sends

RXD low

The demodulator is implemented using precision switched

capacitor techniques The highly critical comparators in the

limiter and discriminator are auto-zeroed for low offset

Carrier Detector

The output of the discriminator is meaningful only if there is

sufficient carrier being received This is established in the

carrier detection circuit which measures the signal on the

line If this exceeds a certain level for a preset period (ad-

justable by the CDT pin) the CD output goes low indicating

that carrier is present Then the carrier detect threshold is

lowered by 3 dB This provides hysteresis ensuring the CD

output remains stable If carrier is lost CD goes high after

the preset delay and the threshold is increased by 3 dB

MODULATOR SECTION

The modulator consists of a frequency synthesizer and a

sine wave synthesizer The frequency synthesizer produces

one of four tones depending on the OA and TXD pins The

frequencies are synthesized to high precision using a crystal

oscillator and variable dual modulus counter

The counters used respond quickly to data changes introduc-

ing negligible bit jitter while maintaining phase coherence

The sine wave synthesizer uses switched capacitors to

‘‘look up’’ the voltages of the sine wave This sampled sig-

nal is then further processed by switched capacitor and

continuous filters to ensure the high spectral purity required

by FCC regulations

Applications Information

TRANSMIT LEVEL ADJUSTMENT

The transmitted power levels of Table II refer to the power

delivered to a 600X load from the external 600X source

impedance The voltage on the load is half the TXA voltage

This should be kept in mind when designing interface cir-

cuits which do not match the load and source inpedances

The transmit level is programmable by placing a resistor

installation to the exchange provide 3 dB of attenuation the

This is the maximum level permitted by most telephone

companies Thus with this programming the MM74HC943

will interface to most telephones This arrangement is called

the ‘‘permissive arrangement’’ The disadvantage with the

permissive arrangement is that when the loss from a phone

to the exchange exceeds 3 dB no compensation is made

and SNR may be unnecessarily degraded

TABLE II Universal Service Order Code Resistor Values

Line

Transmit

Programming

Loss

Level

(dB)

(dBm)

(X)

0

b

12

Open

1

b

11

19800

2

b

10

9200

3

b

9

5490

CARRIER DETECT THRESHOLD ADJUSTMENT

The carrier detect threshold is directly proportional to the

voltage on CDA This pin is connected internally to a high

impedance source This source has a nominal Thevenin

equivalent voltage of 12V and output impedance of 100 kX

By forcing the voltage on CDA the carrier detect threshold

may be adjusted To find the voltage required for a given

threshold the following equation may be used

CARRIER DETECT TIMING ADJUSTMENT

CDT A capacitor on Pin 4 sets the time interval that the

carrier must be present before CD goes low It also

sets the time interval that carrier must be removed

before CD returns high The relevant timing equations

are

DESIGN PRECAUTIONS

Power supplies to digital systems may contain high ampli-

tude spikes and other noise To optimize performance of the

MM74HC943 operating in close proximity to digital systems

supply and ground noise should be minimized This involves

attention to power supply design and circuit board layout

Power supply decoupling close to the device is recommend-

ed Ground loops should be avoided For further discussion

of these subjects see the AudioRadio Handbook published

by National Semiconductor Corporation

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