MP2918

—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER

MP2918 Rev. 1.02

www.MonolithicPower.com

25

5/31/2017

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PCB Layout Guidelines

Efficient

PCB

layout

is

critical

for

stable

operation, especially for the input capacitor

placement. A four-layer layout is strongly

recommended

to

achieve

better

thermal

performance. For best results, refer to Figure

10 and Figure 11 and follow the guidelines

below.

1.

Place the MOSFETs as close as possible

to the device.

2.

Make the sense lines (the red lines in Inner

Layer 2 of Figure 10 and Figure 11) run

close together using a Kelvin connection to

reduce the line drop error.

3.

Use a large ground plane to connect to

PGND directly.

4.

Add vias near PGND if the bottom layer is a

ground plane.

5.

Ensure that the high-current paths at

traces.

6.

Place

the

ceramic

input

capacitor,

especially the small package size (0603)

input bypass capacitor, as close to IN and

PGND

as

possible

to

minimize

high-

frequency noise.

7.

Keep the connection of the input capacitor

and IN as short and wide as possible.

8.

Place the VCC1 capacitor as close to

VCC1 and SGND as possible.

9.

Route SW and BST away from sensitive

analog areas such as FB.

10. Place the feedback resistors close to the

chip

to

ensure

that

the

trace

which

connects to FB is as short as possible.

11. Use multiple vias to connect the power

planes to the internal layers.

Top Layer

Inner Layer 1

Inner Layer 2

Bottom Layer

Figure 10: Recommended PCB Layout for

TSSOP Package

(6)

NOTE:

6)

The recommended PCB layout is based on Figure 12.