MP8846 – 6A, 8V SYNCHRONOUS STEP-DOWN CONVERTER

MP8846 Rev. 1.0

www.MonolithicPower.com

7

5/19/2015

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Parameter

Symbol

Condition

Cb=100pF

Cb=400pF

Units

Min

Max

Min

Max

SCLH and SCL Clock

Frequency

0

3.4

0

0.4

MHz

Set-Up Time for a Repeated

Start Condition

160

-

600

-

ns

Hold Time (Repeated) Start

Condition

160

-

600

-

ns

Low Period of the SCL Clock

160

-

1300

-

ns

High Period of the SCL Clock

60

-

600

-

ns

Data Set-Up Time

10

-

100

-

ns

Data Hold Time

0

70

0

-

ns

Rise Time of SCLH Signal

10

40

20*0.1Cb

300

ns

Rise Time of SCLH Signal

after a Repeated Start

Condition and after an

Acknowledge Bit

10

80

20*0.1Cb

300

ns

Fall Time of SCLH Signal

10

40

20*0.1Cb

300

ns

Rise Time of SDAH Signal

10

80

20*0.1Cb

300

ns

Fall Time of SDAH Signal

10

80

20*0.1Cb

300

ns

Set-Up Time for Stop

Condition

160

-

600

-

ns

Bus-Free Time between a

Stop and Start Condition

160

-

1300

-

ns

Data Valid Time

-

16

-

90

ns

Data Valid Acknowledge

Time

-

160

-

900

ns

Capacitive Load for each Bus

Line

SDAH and SCLH Line

-

100

-

400

pF

SDAH+SDA Line and

SCLH+SCL Line

-

400

-

400

pF

Noise Margin at the Low

Level

For each Connected

Device

-

-

V

Noise Margin at the High

Level

For each Connected

Device

-

-

V

Notes: