MP8847 – 6A, 2.7V-6V, HIGH-EFFICIENCY, SYNCHRONOUS

STEP-DOWN SWITCHER WITH I

MP8847 Rev. 1.02

www.MonolithicPower.com

19

12/28/2017

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2017 MPS. All Rights Reserved.

Figure 3: MP884x Family Control Interface

PGOOD Configuration

The MP8847 has an option to use the

PG_LOHI function. This function can be written

in the Pglohi bit (Reg02 Syscntlreg1 [D2]). The

default value is 1, where PGOOD senses both

a positive and negative excursion of Vo from

the reference. If writing this bit to 0, PGOOD

only senses a negative voltage excursion of Vo

from the reference.

Input Over-Voltage Protection (OVP)

The MP8847 has an option to use the

VIN_OVP function. This function can be written

in theVIN_OVP bit (Reg02 Syscntlreg1 [D1]).

The default value is 0, where the VIN OVP

function is enabled. When VIN is higher than

6.3V, the converter is disabled. After VIN

recovers to 6.2V, the converter restarts. If the

VIN_OVP bit is set to 1, VIN OVP is disable.

The converter will not stop, even if VIN exceeds

its safe range.

Forced Continuous Conduction Mode (CCM)

The

MP8847

has

auto-pulse-frequency

modulation (PFM) mode and forced CCM. This

function can be written in the Mode bit (Reg02

Syscntlreg1 [D0]). The default value is 0, where

auto-PFM mode is selected. Considering a

smaller Vo ripple and regulation for a full load

range, forced CCM is recommended. Set this

bit to 1 to disable PFM mode.

Output Discharge

The MP8847 has an output discharge function.

Writing the Out-dis bit (Reg03 SysCntlreg2 [D4])

can change the output discharge mode. The

default value is 0, and Vo can be discharged by

its load when EN is low. Writing D4=1 can

enable the function, and then the output voltage

can be discharged by the internal pull-down

resistance.

Output Voltage Transition Slew Rate

When the output voltage switches from low to

high or from high to low, the transition slew rate

can be different. There are two possible values

for selection. Through writing the Slew Rate bits

(Reg02 Syscntlreg1[D4: D3]), the transition

slew rate can be set at one possible value

based on the application. The internal reference

follows the set slew rate, but the output voltage

slew rate does not always follow the internal

reference. Considering the output capacitor and