MP8868 – SYNCHRONOUS STEP-DOWN CONVERTER

MP8868 Rev.1.1

www.MonolithicPower.com

7

5/15/2015

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Cb=100pF

Cb=400pF

Parameter

Symbol Condition

Min

Max

Min

Max

Units

SCLH

and

SCL

clock

frequency

0

3.4

0

0.4

MHz

Set-up time for a repeated

START condition

160

-

600

-

ns

Hold time (repeated) START

condition

160

-

600

-

ns

Low period of the SCL clock

160

-

1300

-

ns

High period of the SCL clock

60

-

600

-

ns

Data set-up time

10

-

100

-

ns

Data hold time

0

70

0

-

ns

Rise time of SCLH signal

10

40

20*0.1Cb

300

ns

Rise time of SCLH signal after

a repeated START condition

and after an acknowledge bit

10

80

20*0.1Cb

300

ns

Fall time of SCLH signal

10

40

20*0.1Cb

300

ns

Rise time of SDAH signal

10

80

20*0.1Cb

300

ns

Fall time of SDAH signal

10

80

20*0.1Cb

300

ns

Set-up

time

for

STOP

condition

160

-

600

-

ns

Bus free time between a

STOP and START condition

160

-

1300

-

ns

Data Valid Time

-

16

-

90

ns

Data valid acknowledge time

-

160

-

900

ns

SDAH and SCLH line

-

100

-

400

pF

Capacitive load for each bus

line

SDAH+SDA line and

SCLH+SCL line

-

400

-

400

pF

Noise margin at the LOW

level

For each connected

device

-

-

V

Noise margin at the HIGH

level

For each connected

device

-

-

V

Notes: