MP8869 datasheet(21/37 Pages) MPS

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MP8869

– 17V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER

PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE

MP8869 Rev.1.0

www.MonolithicPower.com

6/8/2016

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

Start-Up and Shutdown

If VIN, VCC, and EN exceed their respective

thresholds, the chip starts up. The reference

block starts first, generating stable reference

voltages and currents, and then the internal

regulator is enabled. The regulator provides a

stable supply for the remaining circuitries.

Several events can shut down the chip: EN low,

VIN low, VCC low, thermal shutdown, OVP

latch,

and

OCP

latch.

the

shutdown

procedure, the signaling path is blocked first to

avoid any fault triggering. VEAO and the internal

supply rail are then pulled down.

2C Control and Default Output Voltage

When the MP8869 is enabled, the output

voltage is determined by the FB resistors with a

programmed soft-start time. Afterward, the I

bus can communicate with the master. If the

chip does not receive an I

2C communication

signal continuously, it can work through FB and

performs behavior similar to a traditional non-

2C part. The output voltage is determined by

the resistor dividers R1, R2, and FB reference

voltage. VOUT can be calculated by Equation (3):

Vout(V)

0.6 (1

)



 

(3)

The FB loop VREF is 0.6V. The FB loop

reference voltage is a fixed value that cannot be

adjusted by the I

2C.

Loop Switch

There is no output slew rate control during the

FB loop to the I

2C loop. When the output

voltage setting is much larger or smaller than

the present voltage, it is recommended to take

two steps to finish the loop switch and output

voltage setting.

During the FB loop to the I

2C loop, first set the

output voltage in the I

2C loop to the present

output voltage, and then set V_BOOT = 0 to

switch the FB loop to the I

2C loop. Second,

change the output voltage to the target with

slew-rate control in the I

2C loop. Please refer to

the Output Voltage Dynamic Scaling section on

page 30 for details.

In the I

2C control loop, the output voltage is

determined by the I

2C control, and the FB

feedback loop is disabled. After the MP8869

receives a valid data byte of the output voltage

setting, the MP8869 adjusts the DAC output as

the reference voltage with a controlled slew rate.

The slew rate is determined by three bits D[5:3]

in register 01.

2C Slave Address

To support multiple devices used on the same

2C bus, A0 can be used to select four different

addresses. A resistor divider from VCC to GND

can achieve an accurate reference voltage.

Connect A0 to this reference voltage to set a

different I

2C slave address (see Figure 6). The

internal

circuit

changes

the

2C address

accordingly. When the master sends an 8-bit

address value, the 7-bit I

2C address should be

followed

0/1

indicate

write/read

operation. Table 2 shows the recommended I

address selection by the A0 voltage.

RA0_up

RA0_down

VCC

2MΩ

Figure 6: I

2C Slave Address Selection Set-Up

Table 2: Recommended I

2C Slave Address

Selection by A0 Resistor Divider

A0 Upper

Resistor

RA0_up(kΩ)

A0 Lower

Resistor

RA0_down (kΩ)

2C Slave Address

Binary

Hex

No connect

110 0000

60H

500

300

110 0010

62H

300

500

110 0100

64H

100

No connect

110 0110

66H

MP8869 Datasheet(PDF) 21 Page - Monolithic Power Systems

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