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MP8869SGL Datasheet(PDF) 28 Page - Monolithic Power Systems |
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MP8869SGL Datasheet(HTML) 28 Page - Monolithic Power Systems |
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28 / 39 page  MP8869S – 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER MP8869S Rev. 1.03 www.MonolithicPower.com 28 1/18/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. 3) Reg02 SysCntlreg2 Register 02 is the second system control register. The highest two bits of the PG deglitch time D[7:6] defines the PG signal rising and falling edge delay times. When output OVP or UVP is triggered, the PG signal turns low or high after a delay time. There are four levels of PG delay time that can be programmed by the I2C in different conditions. The two switching frequency bits D[5:4] are used for switching frequency selection. The MP8869S supports up to 1.25MHz of switching frequency by setting the two bits to 11. The MP8869S maximum programmable switching frequency is limited by internal minimum on- time (see Table 1). The bit soft stop defines the output voltage discharge behavior after EN shutdown. When soft stop is set to 0, the output voltage is not controlled after EN shutdown. When soft stop is set to 1, the output voltage is discharged linearly to zero with the set soft-stop time. The lowest three bits, current limit adjust D[2:0], are used for peak and valley current-limit selection. There are eight levels of current limit that can be selected for different application conditions. NAME BITS DEFAULT DESCRIPTION PG Deglitch Time D[7:6] 11 Power good signal rising and falling edges’ delay time. When FB or VOUT is out of regulation window, the PG comparator is triggered, but needs a delay time before the PG signal can turn high or low. D[7:6] PG Deglitch D[7:6] PG Deglitch 00 <1 μs 10 12 μs 01 6 μs 11 30 μs Switching Frequency D[5:4] 00 Switching frequency set bit. There is no dedicated frequency oscillator inside the part. The switching frequency is fairly fixed by controlling the TON timer. D[5:4] Frequency D[5:4] Frequency 00 500kHz 10 1MHz 01 750kHz 11 1.25MHz Soft Stop D[3] 0 This bit defines the VOUT discharge behavior after EN shutdown. 0 means VOUT is not controlled after EN shutdown. 1 means VOUT is discharged linearly to zero with the set soft-stop time. Current Limit Adjust D[2:0] 001 D[2:0] Valley Current Limit (A) D[2:0] Valley Current Limit (A) 000 16 100 8.5 001 14 101 7 010 12 110 6 011 10 111 5 |
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