MIC2185

Micrel

MIC2185

2

May 2002

Pin Description

Pin Number

Pin Name

Pin Function

1

VINA

Input voltage to control circuitry (2.9V to 14V).

2

SKIP

Skip (Input): Regulator operates in PWM mode (no pulse skipping) when pin

is pulled low, and skip mode when raised to VDD. There is no automatic

switching between PWM and skip mode available on this device.

3

SS

Soft Start (External Component) : Reduces the inrush current and delays

and slows the output voltage rise time. A 5

µA current source will charge the

capacitor up to VDD.

4

COMP

Compensation (Output): Internal error amplifier output. Connect to a

capacitor or series RC network to compensate the regulator’s control loop.

5

SGND

Small Signal Ground (Return) : Must be routed separately from other

grounds to the (–) terminal of C

6

FB

Feedback (Input) : Regulates FB to 1.245V.

7

EN/UVLO

Enable/Undervoltaqe Lockout (Input): A low level on this pin will power down

the device, reducing the quiescent current to under 0.5

µA. This pin has two

separate thresholds, below 1.5V (typical) the output switching is disabled,

and below 0.9V (typical) the device is forced into a complete micropower

shutdown. The 1.5V threshold functions as an accurate undervoltage lockout

(UVLO) with 140mV hysteresis.

8

VREF

Voltage Reference (Output) : The 1.245V reference is available on this pin.

A 0.1

µF capacitor should be connected form this pin to SGnd.

9

CSH

Current Sense (Input) : The (+) input to the current limit comparator. A built

in offset of 100mV (typical) between CSH and SGnd in conjunction with the

current sense resistor sets the current limit threshold level. This is also the

(+) input to the current amplifier.

10

VDD

3V Internal Linear-Regulator (Output) : VDD is also the supply voltage bus

for the chip. Bypass to SGND with 1

µF. Maximum source current is 0.5mA.

11

SYNC

Frequency Synchronization (Input): Connect an external clock signal to

synchronize the oscillator. Leading edge of signal above 1.4V (typical) starts

switching cycle. Connect to SGND if not used.

12

PGND

MOSFET Driver Power Ground (Return) : Connects bottom of current sense

resistor and the (–) terminal of C

13

OUTN

N-Channel Drive (Output) : High current drive for n-channel MOSFET.

Voltage swing is from ground to V

14

OUTP

P-Channel Drive (Output) : High current drive for the synchronous p-channel

MOSFET. Voltage swing is from ground to V

5

Ω.

15

FREQ/2

Frequency Divider (Input) : When this pin is low, the oscillator frequency is

400KHz. When this pin is raised to VDD, the oscillator frequency is 200KHz.

16

VINP

Gate Drive Voltage (Input) : This is the power input to the gate drive circuitry

(2.9V to 14V). This pin is typically connected to the output voltage to

enhance gate drive.

Pin Configuration

1

VINA

SKIP

SS

COMP

SGND

FB

EN/UVLO

VREF

16 VINP

FREQ/2

OUTP

OUTN

PGND

SYNC

VDD

CSH

15

14

13

12

11

10

9

2

3

4

5

6

7

8

16-pin Narrow Body SOP (M)

16-pin QSOP (QS)