MP4088GS datasheet(16/20 Pages) MPS

16 / 20 page

MP4088 – NON

MP4088 Rev. 1.0

11/23/2015

MPS Proprietary Information

PCB Layout Guidelines

Efficient PCB layout is critical

operation, good EMI, and goo

performance, especially in very

applications. For best results, refer

and follow the guidelines below:

1. Keep the loop formed between th

the inductor, the freewheeling dio

output capacitor as small as p

better EMI.

2. Place the AC input far away

switching nodes to minimize

coupling that may bypass the inp

3. Place the VCC capacitor as clo

and GND as possible.

4. Place the feedback resistor as c

as possible to minimize the

sampling loop and minimize

coupling route.

5. If using SOIC-8 EP package IC

to connect the exposed pad to GN

Top Layer

Bottom Layer

Figure 8: Recommended PCB L

N-ISOLATED, TRIAC DIMMABLE PFC LED DR

www.MonolithicPower.com

n. Patent Protected. Unauthorized Photocopy and Duplication Pro

for stable

od thermal

small LED

to Figure 8

he MP4088,

ode, and the

possible for

y from the

the noise

ut filter.

ose to VCC

lose to OVF

e feedback

the noise

C, remember

ND plane.

Layout

Design Example

Table 1 is a design exa

application guidelines base

specifications:

Table 1: Design

VIN

198V

VOUT

IOUT

Figure 9 shows the d

schematic. This circuit is

performance and circuit w

device applications, please

evaluation board datasheets

RIVER FOR 230VAC

ohibited.

ample following the

ed on the following

Example

VAC to 265VAC

55V

100mA

detailed application

used for the typical

aveforms. For more

e refer to the related

MP4088GS Datasheet(PDF) 16 Page - Monolithic Power Systems

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