MP8763D ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER

MP8763D Rev. 1.1

www.MonolithicPower.com

22

1/15/2015

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2015 MPS. All Rights Reserved.

LAYOUT RECOMMENDATION

1. Place high current paths (GND, IN, and SW)

very close to the device with short, direct and

wide traces.

2. Two-layer

IN

copper

layers

are

recommended to achieve better performance.

Respectively put at least a decoupling

capacitor on either side of the IC that has VIN

pin and as close to the IN and GND pins as

possible. Also, several vias with 18mil

diameter

and

8mil

hole-

size

are

recommended to be placed under the device

and are required near input capacitors to help

on the thermal dissipation, also reduce the

parasitic inductance.

3. Put a decoupling capacitor as close to the

VCC and AGND pins as possible.

4. Keep the switching node (SW) plane as small

as possible and far away from the feedback

network.

5. Place the external feedback resistors next to

the FB pin. Make sure that there are no vias

on the FB trace. The feedback resistors

should refer to AGND instead of PGND.

6. Keep the BST voltage path (BST, C3, and

SW) as short as possible.

7. Recommend strongly a four-layer layout to

improve thermal performance.

MP8763D

Figure 13—Schematic Reference for PCB

Layout

B ST

VC C

PG

AG N D

SS

FB

FR EQ

EN

C1 D

Top Layer

Inner1 Layer

Inner2 Layer