ADC12L080 datasheet(17/23 Pages) NSC

17 / 23 page

Functional Description

Operating on a single +3.3V supply, the ADC12L080 uses a

pipeline architecture with error correction circuitry to help

ensure maximum performance.

Differential analog input signals are digitized to 12 bits. Each

analog input signal should have a peak-to-peak voltage

equal to the input reference voltage, V

REF, be centered

around V

REF and be 180˚ out of phase with each other. Table

1 and Table 2 indicate the input to output relationship of the

ADC12L080. Although a differential input signal is required

for rated operation, single-ended operation is possible with

reduced performance if one input is biased to V

REF and the

other input is driven. If the driven input is presented with its

full range signal, there will bea6dB reduction of the output

range, limiting it to the range of 1⁄4 to 3⁄4 of the minimum

output range obtainable if both inputs were driven with com-

plimentary signals. Section 2.2 explains how to avoid this

signal reduction.

TABLE 1. Input to Output Relationship — Differential

Input

IN+

IN−

Output

CM −VREF

CM +VREF

0000 0000 0000

CM −0.5 * VREF

CM +0.5 * VREF

0100 0000 0000

1000 0000 0000

CM +0.5 * VREF

CM −0.5 * VREF

1100 0000 0000

CM +VREF

CM −VREF

1111 1111 1111

TABLE 2. Input to Output Relationship — Single-Ended

Input

IN+

IN−

Output

CM −2*VREF

0000 0000 0000

CM −VREF

0100 0000 0000

1000 0000 0000

CM +VREF

1100 0000 0000

CM +2*VREF

1111 1111 1111

The output word rate is the same as the clock frequency,

which may be in within the range indicated in the Electrical

Tables. The analog input voltage is acquired at the rising

edge of the clock and the digital data for that sample is

delayed by the pipeline for 6 clock cycles.

A logic high on the power down (PD) pin reduces the con-

verter power consumption to 50 mW.

Applications Information

1.0 OPERATING CONDITIONS

We recommend that the conditions in the Operating Table be

observed for operation of the ADC12L080.

2.0 ANALOG INPUTS

The ADC12L080 has two analog signal inputs, V

IN+ and

IN−, which form a differential input pair. There is one refer-

ence input pin, V

REF.

2.1 Reference Pins

The ADC12L080 can be used with the internal 1.0V refer-

ence or with an external reference. While designed and

specified to operate with a 1.0V reference, the ADC12L080

performs well with reference voltages in the range of indi-

cated in the Operating Ratings table. Lower reference volt-

ages will decrease the signal-to-noise ratio (SNR) of the

ADC12L080. Higher reference voltages (and input signal

swing) will degrade THD performance for a full-scale input.

An input voltage below 2.0V at pin 1 (V

REF) is interpreted to

be an external reference and is used as such. Connecting

this pin to the analog supply (V

A) will force the use of the

internal 1.0V reference.

It is very important that all grounds associated with the

reference voltage and the input signal make connection to

the analog ground plane at a single, quiet point to minimize

the effects of noise currents in the ground path.

The reference input pin serves two functions. When the input

at this pin at or below 2V, this voltage is accepted as the

reference for the converter. When this voltage is connected

to V

A, then internal 1.0V reference is used. Functionality is

undefined with voltages at this pin between 2V and V

The three Reference Bypass Pins (V

RP,VRM and VRN) are

made available for bypass purposes only. These pins should

each be bypassed to ground with a 0.1 µF capacitor, and a

1.0 µF should be connected from V

RP to VRN. Higher capaci-

tances will result in a longer power down exit cycle. Lower

capacitances may result in degraded dynamic performance.

DO NOT LOAD these pins.

2.2 Signal Inputs

The signal inputs are V

IN+ and VIN−. The input signal, VIN,is

defined as

IN =(VIN+)– (VIN−)

Figure 2 shows the expected input signal range. Note that

the nominal input common mode voltage, V

CM,isVA/2 and

the nominal input signals each run between the limits of

AGND and V

REF. The Peaks of the input signals should

never exceed the voltage described as

Peak Input Voltage = V

A − 0.5V

to maintain dynamic performance.

The ADC12L080 performs best with a differential input, each

of which should be centered around a common mode volt-

age, V

CM. The peak-to-peak voltage swing at both VIN+ and

IN− should not exceed the value of the reference voltage or

the output data will be clipped. The two input signals should

be exactly 180˚ out of phase from each other and of the

same amplitude. For single frequency inputs, angular errors

result in a reduction of the effective full scale input. For a

complex waveform, however, angular errors will result in

distortion.

20061011

FIGURE 2. Expected Input Signal Range

ADC12L080 Datasheet(PDF) 17 Page - National Semiconductor (TI)

ADC12L080 Datasheet(HTML) 17 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL