LTM2886

22

2886fb

For more information www.linear.com/LTM2886

Table 2. Bidirectional SPI Timing Event Description

TIME

CPHA

EVENT DESCRIPTION

0, 1

Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. Logic side slave data output

enabled, initial data is not equivalent to slave device data output

0, 1

Propagation delay chip select, logic to isolated side, 50ns typical

0, 1

Slave device chip select output data enable

0

Start of data transmission, data set-up

1

Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge

0, 1

Propagation delay of slave data, isolated to logic side, 50ns typical

0, 1

Slave data output valid, logic side

0

Propagation delay of data, logic side to isolated side

1

Propagation delay of data and clock, logic side to isolated side

0, 1

Logic side data sample time, half clock period delay from data set-up transition

0, 1

Propagation delay of clock, logic to isolated side

0, 1

Isolated side data sample time

0, 1

Synchronous data and clock transition, logic side

0, 1

Data to clock delay, must be ≤13ns

0, 1

Clock to data delay, must be ≤3ns

0, 1

Propagation delay clock and data, logic to isolated side

0, 1

Slave device data transition

0, 1

Propagation delay slave data, isolated to logic side

0, 1

Slave data output to sample clock set-up time

0

Last data and clock transition logic side

1

Last sample clock transition logic side

0

Propagation delay data and clock, logic to isolated side

1

Propagation delay clock, logic to isolated side

0

Last slave data output transition logic side

1

Last slave data output and data transition, logic side

1

Propagation delay data, logic to isolated side

0, 1

Asynchronous chip select transition, end of transmission. Disable slave data output logic side

0, 1

Chip select transition isolated side, slave data output disabled

APPLICATIONS INFORMATION

terface. Clock (SCL) is unidirectional, supporting master

mode only, and data (SDA) is bidirectional. The maximum

is detailed in Figure 10. The data rate is limited by the slave

clock propagation delay of 225ns, glitch filter and isolated

data delay of 500ns maximum, and the combined isolated

and logic data fall time of 300ns at maximum bus loading.

toamaximumof175ns,guaranteeingsufficientdatasetup

The isolated side bidirectional serial data pin, SDA2,

simplified schematic is shown in Figure 11. An internal

1.8mA current source provides a pull-up for SDA2. Do not

connect any other pull-up device to SDA2. This current

source is sufficient to satisfy the system requirements for

bus capacitances greater than 200pF in FAST mode and

greater than 400pF in STANDARD mode.