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LTC7800

7800f

For more information www.linear.com/LTC7800

Note that the LTC7800 can only be synchronized to an

external clock whose frequency is within range of the

LTC7800’sinternalVCO,whichisguaranteedtobebetween

320kHz and 2.25MHz. Typically, the external clock (on the

PLLIN/MODE pin) input high threshold is 1.6V, while the

input low threshold is 1.1V. The LTC7800 is guaranteed

to synchronize to an external clock that swings up to at

least 2.5V and down to 0.5V or less.

RapidphaselockingcanbeachievedbyusingtheFREQpin

to set a free-running frequency near the desired synchro-

nization frequency. The VCO’s input voltage is prebiased

at a frequency corresponding to the frequency set by the

FREQ pin. Once prebiased, the PLL only needs to adjust

the frequency slightly to achieve phase lock and synchro-

nization. Although it is not required that the free-running

frequency be near external clock frequency, doing so will

prevent the operating frequency from passing through a

large range of frequencies as the PLL locks.

APPLICATIONS INFORMATION

Table 2 summarizes the different states in which the FREQ

pin can be used.

Table 2

FREQ PIN

PLLIN/MODE PIN

FREQUENCY

DC Voltage

0.94MHz

INTVCC

DC Voltage

1.44MHz

Resistor

DC Voltage

320kHz to 2.25MHz

Any of the Above

External Clock

Phase Locked to

External Clock

Minimum On-Time Considerations

Minimum on-time, tON(MIN), is the smallest time duration

that the LTC7800 is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

tON(MIN) <

VOUT

VIN f

( )

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

The minimum on-time for the LTC7800 is approximately

45ns. However, as the peak sense voltage decreases the

minimum on-time gradually increases up to about 70ns.

This is of particular concern in forced continuous applica-

tions with low ripple current at light loads. If the duty cycle

drops below the minimum on-time limit in this situation,

a significant amount of cycle skipping can occur with cor-

respondingly larger current and voltage ripple.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

FREQ PIN RESISTOR (k)

7800 F08

95 105

250

500

750

1000

1250

1500

1750

2000

2250

Figure 8. Relationship Between Oscillator Frequency and

Resistor Value at the FREQ Pin

If the PLLIN/MODE pin is not being driven by an external

clock source, the FREQ pin can be tied to SGND, tied to

INTVCCorprogrammedthroughanexternalresistor.Tying

FREQtoSGNDselects0.94MHzwhiletyingFREQtoINTVCC

selects 1.44MHz. Placing a resistor between FREQ and

SGND allows the frequency to be programmed between

320kHz and 2.25MHz, as shown in Figure 8.

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