LTC3255 datasheet(20/28 Pages) LINER

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LTC7820

7820fc

For more information www.linear.com/LTC7820

APPLICATIONS INFORMATION

Design Example

As a design example using LTC7820 for a high voltage

high power voltage divider, assume VIN = 48V (nominal),

VIN = 55V (maximum), VOUT = 24V (nominal), IOUT = 15A

(maximum).

For high power and high voltage applications, always start

withalowswitchingfrequencye.g.200kHztominimizethe

switching losses. To set the 200kHz switching frequency,

a 60.4k/1% resistor is connected from Freq pin to ground.

Setting the CFLY voltage ripple to be 2% of the output

voltage is a good starting point with trade-off between

efficiency and power density. The CFLY can be calculated

based on the equation below:

CFLY =

IOUT(MAX)

2fSVCFLY(RIPPLE)

15A

2 • 200kHz • 0.48V

= 78.125µF

Considering the ceramic capacitance derating at 24V DC

bias voltage, 16 of 10µF/X7R/50V ceramic capacitors are

paralleledasflyingcapacitors.TheworstcaseRMScurrent

may be 40% higher than the maximum output current. So

the worst case RMS on each capacitor can be estimated

by this equation:

IRMS(MAX) =

IOUT(MAX) •140%

15A • 140%

= 1.3125A

where N is the number of flying capacitors. Double check

and make sure the RMS current on each capacitor is below

the ripple current ratings and temperature rise is below

the limits.

The output capacitor selection is similar to the flying

capacitor selection. More output capacitors resulting

smaller output voltage ripple. Because of the lower RMS

current, the output capacitor value can be much less than

the flying capacitor. Some of the capacitors may be con-

nected between input and output to serve as input/output

capacitorsatthesametime,asshowninFigure6.However

the voltage rating of those capacitors has to be selected

based on the input voltage instead of the output voltage.

ForMOSFETselection,thetopMOSFETM1draintosource

voltage has to be higher than the maximum input voltage,

while the other three MOSFETs drain to source voltage

only needs to be higher than half of the maximum input

voltage. Since logic level FETs are preferred, an Infineon

BSC100N06LS is chosen as the top MOSFET M1 and

BSC032N04LS are used as M2/3/4. Based on the output

resistance equation in the application section, the output

resistance is around 20mΩ, which will result 300mV drop

at the 24V output at 15A load current. In reality, due to

the finite dead time and parasitic resistance on the PCB,

the voltage drop may be higher than the calculated value.

Taking into account the output voltage ripple, a window

comparator with ±1V programmed hysteresis is used to

monitor the output voltage and compares it with the half

of the input voltage during operation. To set the 1V hys-

teresis,a100k/1%resistorisconnectedfromHYS_PRGM

pin to ground.

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