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LT3667

3667fb

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APPLICATIONS INFORMATION

Synchronization (QFN Only)

Synchronizing the oscillator of the LT3667 to an external

frequency can be done by connecting a digital clock signal

to the SYNC pin. The LT3667 then synchronizes its SW

node to the rising edge of this clock signal, as shown in

Figure 4. The square wave amplitude should have valleys

that are below 0.5V and peaks that are above 1.2V (up to

6V), and its on-time and off-time should not fall below

50ns. There is a time delay of typically 280ns between the

rising edge of SYNC and the rising edge of SW which is

in part caused by the minimum switch off-time. The fall-

ing edge of SW is sensitive to the falling edge of SYNC,

it is therefore recommended to adjust the duty cycle of

the SYNC clock signal accordingly to keep its on-time as

short as possible. Alternatively, AC coupling as shown in

Figure 5 can be used to shorten the clock signal's on-time.

from SYNC to ground which will draw current.

TheLT3667maybesynchronizedovera300kHzto2.2MHz

range.TheRTresistorshouldbechosentosettheswitching

frequency 20% below the lowest synchronization input.

For example, if the synchronization signal is 360kHz, RT

should be chosen for 300kHz. Since RT also sets the slope

compensationwhichavoidssubharmonicoscillations,the

minimum inductor value must be calculated using the

frequency determined by RT.

UVLO1 Pin (QFN Only)

TheswitchingregulatorpartoftheLT3667canbeindepen-

dently disabled via the UVLO1 pin. The falling threshold of

the UVLO1 comparator is 1V, with a 75mV hysteresis. The

UVLO1 pin has no effect if VIN1 and VIN2 are below 4.3V,

because then the internal undervoltage lockout keeps the

LT3667 shut down anyway.

Adding a resistive divider from IN1 to UVLO1 as shown

in Figure 6 programs the LT3667 to enable the switching

regulator only when VIN1 is above a certain threshold

voltage VIN(UVLO1), given by:

VIN(UVLO1) =

R1+R2

•1V

Notethatduetothecomparator’shysteresis,theswitching

regulator will not be enabled until the input rises slightly

above VIN(UVLO1).

Figure 6. UVLO1 Pin Allows Programmable Undervoltage

Lockout or Independent Disable of the Switching Regulator

3667 F04

200ns/DIV

VSYNC

2V/DIV

RINSING

SYNC

TRIGGERS

VSW

5V/DIV

FRONT PAGE APPLICATION

SYNC

10k

3667 F05

10pF

3.3V

LT3667

GND

Figure 4. Synchronization Waveforms

Figure 5. Example of AC Coupling of SYNC Clock Signal

The LT3667 still enters Burst Mode operation at low

output loads while synchronized to an external clock, but

the burst pulses are synchronized to that clock signal. If

synchronization is not needed, the SYNC pin should be

grounded. It may also be tied to a voltage above 1.2V

(logic high), but note that there is an internal 4M resistor

–

SWITCHING

REGULATOR

SHUT DOWN

UVLO1

LT3667

IN1

VIN1

3667 F06

Shorted and Reversed Input Protection

If the inductor is chosen so that it won’t saturate exces-

sively, the switching regulator will tolerate a shorted

output. There is another situation to consider in systems

where the output will be held high when the input to the

LT3667 is absent. This may occur in battery charging

applications or in battery backup systems where a battery

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