LTC1150 datasheet(12/24 Pages) LINER

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LTC2758

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operaTion

data occupies the first 18 bits of the 24-bit field; and the

span bits are the last four bits of the second data byte

when checking the output range. In both cases, all other

bits in the 24-bit data field are filled by zeros. Figure 2

shows the input and readback sequences.

The data outputted by SRO is always in the same position

and sequence as the input data. Note, however, that this

means that the SRO data shifts out one-half clock cycle

earlier than the corresponding bit shifting in on SDI. For

example, code bit D9, which is shifted in to SDI on the

rising edge of SCK clock 17, is clocked out of SRO on the

falling edge of clock 16. This allows D9 to be clocked to an

external microprocessor on the rising edge of clock 17.

For Read commands, the requested data is shifted out

of SRO in the 3-byte (24-bit) data field immediately after

the command/address byte. There is no instruction-cycle

latencyforReadcommands;thedatashiftsoutinthesame

instruction cycle in which it was requested.

For non-read (i.e., Write and/or Update) commands, SRO

automatically shifts out the contents of the buffer that

was acted upon in the preceding command. This “rolling

readback” default mode of operation can dramatically re-

duce the number of instruction cycles needed, since most

commands can be verified during subsequent commands

with no additional overhead. A conceptual flow diagram

is shown in Figure 3. Table 1 shows, for each anteced-

ent command, which register (‘readback pointer’) will be

copiedintotheReadbackregisterandoutputtedfromSRO

during the following instruction cycle.

Span Readback in Manual Span Configuration

If a Span DAC register is chosen for readback, SRO re-

sponds by outputting the actual output span; this is true

whether the LTC2758 is configured for SoftSpan (M-SPAN

tied to GND) or manual span (M-SPAN tied to VDD).

In SoftSpan configuration, SRO outputs the span code

from the Span DAC register (programmed through the

SPI port). In manual span configuration, the active output

range is controlled by pins S2, S1 and S0, so SRO outputs

the logic values of these pins. The span code bits S2, S1

and S0 always appear in the same order and positions in

the SRO output sequence; see Figure 2.

Serial Interface

When the CS/LD pin is taken low, the data on the SDI pin

is loaded into the shift register on the rising edge of the

clock (SCK pin). The loading sequence required for the

LTC2758 is one byte consisting of a 4-bit command word

(C3 C2 C1 C0) and a 4-bit address word (A3 A2 A1 A0),

then three bytes (24 bits) of data.

When writing a code, the code data is left (MSB) justified;

so that the 24-bit data field consists of 18 code bits fol-

lowed by 6 don’t-care bits.

When writing an output range, the span data should oc-

cupy the last 4 bits of the second data byte, ordered S3

through S0. Figure 2 shows the SDI input word syntax

for writing.

When CS/LD is low, the SRO pin (Serial Readback Output)

is an active output. The readback data begins after the

command (C3-C0) and address (A3-A0) words have been

shifted in to SDI. SRO outputs a logic low from the falling

edge of CS/LD until the Readback data begins.

When CS/LD is high, the SRO pin presents a high imped-

ance (three-state) output.

LDAC is an asynchronous update pin. When LDAC is

taken low, all DACs are updated with code and span data

(data in the Input buffers is copied into the DAC buffers).

CS/LD must be high during this operation; otherwise

LDAC is locked out and will have no effect. The use of

LDAC is functionally identical to the “Update All DACs”

serial input command.

The codes for the command (C3-C0) are defined in Table 1;

Table 2 defines the codes for the address (A3-A0).

Readback

In addition to the Code and Span register sets, each DAC

hasoneReadbackregisterassociatedwithit.Everyinstruc-

tion cycle, the contents of one of the on-chip registers is

copied into a Readback register and serially shifted out

through the SRO pin.

Readback data always appears in the 24-bit data field,

starting on the falling SCK edge immediately after the last

address bit is shifted in on SDI. When reading a code, code

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