HSP50214BVC datasheet(40/62 Pages) RENESAS

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HSP50214B

FN4450 Rev 4.00

Page 40 of 62

May 1, 2007

FIFO Operation Via 8-Bit

Processor

Interface

The Buffer RAM Output may also be accessed via the 8-bit

microprocessor interface C(7:0). Figure 41 shows the

conceptual configuration of the 8-bit

processor interface.

Control Word 20, Bit 24 must be set to 0 in order to obtain

Buffer RAM data to this output. The Microprocessor Read

Section describes how to read the data from each sample

out of the C(7:0) interface.

Recall that INTRRP stays low for 8 PROCCLK cycles. The

FIFO can be read before the INTRRP signal goes low; the

number of samples in the FIFO must be monitored by the user.

The timing relationship of the INTRRP to the snapshot data is

shown in Figure 42.

The read pointer of the FIFO is incremented when Control

Word 23 is written to. The data cannot be read from the

next sample until 4 PROCCLKs after the Buffer RAM

pointer has been incremented. Control Word 22 is used to

reset the Read and Write pointers of the Buffer RAM output

to the first sample to 000 and 007 for write and read

respectively.

FIGURE 40A. FIFO DEPTH IS (WRITE - READ)

FIGURE 40B. FIFO FULL IS WHEN (WRITE - READ) = 7

FIGURE 40C. FIFO EMPTY IS WHEN (WRITE - READ) = 1

FIGURE 40D. FIFO READY IS WHEN (WRITE - READ) > DEPTH

FIGURE 40.

WRITE

READ

WRITE

FIFO

DEPTH

WRITE

READ

WRITE

READY

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