ISL59830IA datasheet(14/15 Pages) RENESAS

14 / 15 page

ISL59830

FN7489 Rev.1.00

Page 14 of 15

May 4, 2006

By setting the two PDMAX equations equal to each other, we

can solve the output current and RLOAD to avoid the device

overheat.

Power Supply Bypassing and Printed Circuit Board

Layout

Strip line design techniques are recommended for the input

and output signal traces. As with any high frequency device, a

good printed circuit board layout is necessary for optimum

performance. Lead lengths should be as short as possible. The

power supply pin must be well bypassed to reduce the risk of

oscillation. For normal single supply operation, where the VS-

pin is connected to the ground plane, a single 4.7µF tantalum

capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to

GND will suffice. This same capacitor combination should be

placed at each supply pin to ground if split-internal supplies are

to be used. In this case, the VS- pin becomes the negative

supply rail.

For good AC performance, parasitic capacitance should be

kept to a minimum. Use of wire-wound resistors should be

avoided because of their additional series inductance. Use of

sockets should also be avoided if possible. Sockets add

parasitic inductance and capacitance can result in

compromised performance. Minimizing parasitic capacitance

at the amplifier's inverting input pin is also very important.

ISL59830IA Datasheet(PDF) 14 Page - Renesas Technology Corp