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TLE8457BLE Datasheet(PDF) 17 Page - Infineon Technologies AG |
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TLE8457BLE Datasheet(HTML) 17 Page - Infineon Technologies AG |
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17 / 33 page ![]() Data Sheet 17 Rev. 1.0 2016-08-05 TLE8457 LIN Transceiver with integrated Voltage Regulator Functional Description 4.5 LIN Transceiver The LIN interface is a single wire, bi-directional bus, used for in-vehicle networks. The integrated LIN transceiver of the TLE8457 is the interface between the microcontroller and the physical LIN bus (see Figure 18). Data from the microcontroller is driven to the LIN bus via the TxD input. The transmit data stream on the TxD input is converted to a LIN bus signal with optimized slew rates in order to minimize the electromagnetic emission of the LIN network. The RxD output reads back the information from the LIN bus to the microcontroller. The receiver has an integrated filter network for noise suppression from the LIN bus and to increase the electromagnetic immunity level of the transceiver. The LIN specification defines two valid bus levels (see Figure 14): • Dominant state with the LIN bus voltage level near GND, actively driven by a transceiver. • Recessive state with the LIN bus voltage pulled up to the supply voltage VS through the bus termination. By setting the TxD input of the TLE8457 to a logical “low” signal, the transceiver generates a dominant level on the BUS interface pin. The receiver reads back the signal on the LIN bus and indicates the dominant LIN bus signal with a logical “low” on the RxD output to the microcontroller. By setting the TxD input “high”, the transceiver sets the LIN interface pin to the recessive level. At the same time the recessive level on the LIN bus is indicated by a logical “high” signal on the RxD output. Every LIN network consists of a master node and one or more slave nodes. To configure the TLE8457 for master node applications, a termination resistor of 1 kΩ and a diode must be connected between the LIN bus and the power supply VS (see Figure 18). Figure 14 LIN bus signals TLE8457_LIN_COMMUNICATION_A t TxD VCC BUS VS Recessive Dominant Recessive t t RxD VCC Vth_REC Vth_DOM |
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