ICM7243BLPLZ datasheet(14/17 Pages) RENESAS

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ICM7243

FN3162 Rev 5.00

Page 14 of 17

October 2, 2015

Detailed Description

WR, CS, CS

These pins are immediately functionally ANDed, so all

actions described as occurring on an edge of WR, with CS

and CS enabled, will occur on the equivalent (last) enabling

or (first) disabling edge of any of these inputs. The delays

from CS pins are slightly (about 5ns) greater than from WR

or CS due to the additional inverter required on the former.

MODE

The MODE pin input is latched on the falling edge of WR

(or its equivalent, see above). The location (in Data

Memory) where incoming data will be placed is determined

either from the Address pins or the Sequential Address

Counter. This is controlled by MODE input. MODE also

controls the function of A0/SEN, A1/CLR, and A2/DlSPlay

FULL lines.

Random Access Mode

When the internal mode latch is set for Random Access

(RA) (MODE latched low), the Address input on A0, A1 and

A2 will be latched by the falling edge of WR (or its

equivalent). Subsequent changes on the Address lines will

not affect device operation. This allows use of a

multiplexed 6-bit bus controlling both address and data,

with timing controlled by WR.

Sequential Access Mode

If the internal latch is set for Sequential Access (SA),

(MODE latched high), the Serial ENable input or SEN will

be latched on the falling edge of WR (or its equivalent). The

CLR input is asynchronous, and will force-clear the

Sequential Address Counter to address 000 (CHARacter

1), and set all Data Memory contents to 100000 (blank) at

any time. The DISPlay FULL output will be active in SA

mode to indicate the overflow status of the Sequential

Address Counter. If this output is low, and SEN is (latched)

high, the contents of the Counter will be used to establish

the Data Memory location for the Data input. The Counter

is then incremented on the rising edge of WR. If SEN is

low, or DISPlay FULL is high, no action will occur. This

allows easy “daisy-chaining” of display drivers for multiple

character displays in a Sequential Access mode.

Changing Modes

Care must be exercised in any application involving

changing from one mode to another. The change will occur

only on a falling edge of WR (or its equivalent). When

changing mode from Sequential Access to Random

Access, note that A2/DlSPlay FULL will be an output until

WR has fallen low, and an Address drive here could cause

a conflict. When changing from Random Access to

Sequential Access, A1/CLR should be high to avoid

inadvertent clearing of the Data Memory and Sequential

Address Counter. DISPlay FULL will become active

immediately after the rising edge of WR.

Data Entry

The input Data is latched on the rising edge of WR (or its

equivalent) and then stored in the Data Memory location

determined as described above. The six Data bits can be

multiplexed with the Address information on the same lines

in Random Access mode. Timing is controlled by the WR

input.

OSC/OFF

The device includes a relaxation oscillator with an internal

capacitor and a nominal frequency of 200kHz. By adding

external capacitance to VDD at the OSC/OFF pin, this

frequency can be reduced as far as desired. Alternatively,

an external signal can be injected on this pin. The oscillator

(or external) frequency is pre-divided by 64, and then

further divided by 8 in the Multiplex Counter, to drive the

CHARacter drive lines (see Figure 3). An inter-character

blanking signal is derived from the pre-divider. An

additional comparator on the OSC/OFF input detects a

level lower than the relaxation oscillator's range, and

blanks the display, disables the DISPlay FULL output (if

active), and clears the pre-divider and Multiplex Counter.

This puts the circuit in a low-power-dissipation mode in

which all outputs are effectively open circuits, except for

parasitic diodes to the supply lines. Thus a display

connected to the output may be driven by another circuit

(including another ICM7243) without driver conflicts.

Display Output

The output of the Multiplex Counter is decoded and

multiplexed into the address input of the Data Memory,

except during WR operations (in Sequential Access mode,

with SEN high and DISPlay FULL low), when it scans

through the display data. The address decoder also drives

the CHARacter outputs, except during the inter-character

blanking interval (nominally about 5

s). Each CHARacter

output lasts nominally about 300

s, and is repeated

nominally every 2.5ms, i.e., at a 400Hz rate (times are

based on internal oscillator without external capacitor).

The 6 bits read from the Data Memory are decoded in the

ROM to the 17 (15 for ICM7243B) segment signals, which

drive the SEGment outputs. Both CHARacter and

SEGment outputs are disabled during WR operations (with

SEN high and DISPlay FULL Low for Sequential Access

mode). The outputs may also be disabled by pulling

OSC/OFF low.

The decode pattern from 6 bits to 17 (15) segments is done

by a ROM pattern according to the ASCll font shown.

Custom decode patterns can be arranged, within these

limitations, by consultation with the factory.

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