ISL8240MEVAL3Z datasheet(21/31 Pages) RENESAS

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ISL8240M

FN8450 Rev 2.00

Page 21 of 31

January 7, 2015

Application Information

Programming the Output Voltage

The ISL8240M has an internal 0.6V ±0.7% reference voltage.

Programming the output voltage requires a resistor divider (R1

and R2) between the VOUT, VSEN+, and VSEN- pins, as shown in

Figure 23 on page 14. Please note that the output voltage

accuracy is also dependent on the resistor accuracy of R1 and

R2. The user needs to select a high accuracy resistor (i.e., 0.5%)

in order to achieve the overall output accuracy. The output

voltage can be calculated as shown in Equation 1:

Note: It is recommended to use a 1kΩ value for the top resistor,

R1. The value of the bottom resistor for different output voltages

is shown in Table 4.

At higher output voltage, the inductor ripple increases, which makes

both output ripple and inductor power loss higher. Refer to

Figure 34 on page 24 to choose RSYNC which adjusts the switching

frequency.

Selection of Input Capacitor

Selection of the input filter capacitor is based on how much

ripple the supply can tolerate on the DC input line. The larger the

capacitor, the less ripple expected, however, consideration

should be given to the higher surge current during power-up. The

ISL8240M provides a soft-start function that controls and limits

the current surge.

A combination of bulk capacitors and low Equivalent Series

Resistance (ESR) ceramic capacitors are recommended as input

capacitors. The minimum value of the input ceramic capacitors

can be calculated as shown in Equation 2:

where:

•CIN(CER, MIN) is the minimum required input ceramic

capacitance (µF)

•IO is the output current (A)

• D is the duty cycle

•VP-P is the allowable peak-to-peak voltage (V)

•fSW is the switching frequency (Hz)

The low Equivalent Series Resistance (ESR) ceramic capacitance

is recommended to decouple between the VIN and PGND of each

channel. See Table 2 for some recommended capacitors. This

capacitance reduces voltage ringing created by the switching

current across parasitic circuit elements. All these ceramic

capacitors should be placed as closely as possible to the module

pins. The estimated RMS current should be considered in

choosing ceramic capacitors.

Each 10µF X5R or X7R ceramic capacitor is typically good for 2A

to 3A of RMS ripple current. Refer to the capacitor vendor to

check the RMS current ratings. In a typical 15A output

application for one channel, if the duty cycle is 0.5, it needs at

least three 10µF X5R or X7R ceramic input capacitors.

Selection of Output Capacitors

The ISL8240M is designed for low-output voltage ripple. The

output voltage ripple and transient requirements can be met with

bulk output capacitors (COUT) that have adequately low ESR.

COUT can be a low ESR tantalum capacitor, a low ESR polymer

capacitor or a ceramic capacitor. The typical capacitance is

330µF, and decoupling ceramic output capacitors are used for

each phase. See Tables 1 and 2 for more capacitor information.

Internally optimized loop compensation provides sufficient

stability margins for all ceramic capacitor applications, with a

recommended total value of 700µF per phase. Additional output

filtering may be needed if further reduction of output ripple or

dynamic transient spike is required.

EN/FF Turn ON/OFF

Each output of the ISL8240M can be turned on/off

independently through the EN/FF pins. For parallel use, tie all

EN/FF pins together. Since this pin has the feed-forward function,

the voltage on this pin can actively adjust the loop gain to be

constant for variable input voltage. Please refer to Table 1 on

page 19 to select the resistor divider for commonly used

conditions. Otherwise, use the following procedures to finish the

EN/FF design:

1. A resistor divider from VIN to GND is recommended to set the

EN/FF voltage between 1.25V to 5.0V. The resistor divider

ratio is recommended to be between 3/1 to 4/1 with a

resistor divider at 7.15kΩ/2.05kΩ.

2. Check EN turn-on hysteresis (recommend VEN_HYS >0.3V) :

where:

•RUP is the top resistor of the resistor divider

• N is the total number of the EN/FF pins tied to the resistor divider

TABLE 4. VALUE OF BOTTOM RESISTOR FOR DIFFERENT OUTPUT

VOLTAGES (VOUT vs R2)

(Ω)

VOUT

(V)

(Ω)

0.6

Open

0.8

3.01k

1.0

1.50k

1.2

1.00k

1.5

665

1.8

499

2.0

422

2.5

316

VOUT

0.6

--------







(EQ. 1)

CIN CER MIN





IO D1 D

–





VP-P fSW



-----------------------------------

(EQ. 2)

IIN RMS



Io D 1 D

–





---------------------------------

(EQ. 3)

VEN HYS

–



UP 3x10

–



(EQ. 4)

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