ISL8270MEVAL1Z datasheet(20/56 Pages) RENESAS

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ISL8270M

FN8635 Rev.4.00

Page 20 of 56

Aug 17, 2017

Snapshot Parameter Capture

The ISL8270M offers a special feature to capture parametric data

and some fault status’ following a fault. A detailed description is

provided in “SNAPSHOT (EAh)” on page 47.

Nonvolatile Memory

The ISL8270M has an internal nonvolatile memory that shows

user configurations. Integrated security measures ensure that

the user can only restore the module to a level that has been

made available to them. During the initialization process, the

ISL8270M checks for stored values contained in its internal

nonvolatile memory.

Modules are shipped with factory defaults configurations and

most settings can be overwritten with PMBus commands and

can be stored in nonvolatile memory with the PMBus command

STORE_USER_ALL.

PCB Layout Guidelines

To achieve stable operation, low losses, and good thermal

performance, some layout considerations are necessary.

• For VDD > 6V, the recommended PCB layout is shown in

Figure 29. Leave V25, VDDC, VR5, and VR6 as no connect.

• For 5.5V

 VDD  6V, connect the VDDC pin to the VR6 pin. For

4.5

 VDD < 5.5V, connect the VDDC pin to the VR6 and VR5

pins. An RC filter is required at the input of the VDRVIN pin if

the input supply is shared with the VIN pin.

• Establish separate SGND and PGND planes, then connect the

SGND to PGND planes as shown in Figure 30 in the middle

layer. For making connections between SGND/PGND on the

top layer and other layers, use multiple vias for each pin to

connect to the inner SGND/PGND layer. Do not connect SGND

directly to PGND on a top layer. Connecting SGND directly to

PGND without establishing the SGND plane will bypass the

decoupling capacitor at internal reference supplies, making

the controller susceptible to noise.

• Place enough ceramic capacitors between VIN and PGND,

VOUT and PGND and bypass capacitors between VDD and the

ground plane, as close to the module as possible to minimize

high frequency noise.

• Use large copper areas for the power path (VIN, PGND, VOUT)

to minimize conduction loss and thermal stress. Also, use

multiple vias to connect the power planes in different layers.

Extra ceramic capacitors at VIN and VOUT can be placed on the

bottom layer under VIN and VOUT pads when multiple vias are

used for connecting copper pads on top and bottom layers.

• Connect differential remote sensing traces to the regulation point

to achieve a tight output voltage regulation. Route a trace from

and VSEN+ to the point-of-load where the tight output voltage is

desired. Avoid routing any sensitive signal traces, such as the

VSENSE signal near VSWH pads.

• For noise sensitive applications, it is recommended to connect

VSWH pads only on the top layer, but thermal performance

gets sacrificed. External airflow might be required to keep the

module heat at desired levels. For applications in which

switching noise is less critical, excellent thermal performance

can be achieved in the ISL8270M module by increasing copper

mass attached to the VSWH pad. To increase copper mass on

the VSWH node, create copper islands in the middle and

bottom layers under the VSWH pad and connect them to the

top layer with multiple vias. Make sure to shield those copper

islands with a PGND layer to avoid any interference to noise

sensitive signals.

SYNC

XTEMP+

VSEN -

XTEMP -

VTRK+

VSEN+

VTRK -

VDD

SGND

PGND

UVLO

PGND

PHASE

PGND

SGND

PGND

DDC

VDRVOUT

VDRVIN

CVOUT

FIGURE 29. RECOMMENDED LAYOUT - TOP PCB LAYER

PGND

Connect SGND to PGND

in the middle layer

SGND

PGND

FIGURE 30. RECOMMENDED LAYOUT - CONNECT SGND TO PGND IN

THE MIDDLE PCB LAYER AFTER ESTABLISHING

SEPARATE SGND AND PGND

ISL8270MEVAL1Z Datasheet(PDF) 20 Page - Renesas Technology Corp

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