VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8121

2.488GHz SONET/SDH

Clock Generator

G52163-0, Rev 4.2

Page 1

04/16/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Features

General Description

The VSC8121 is a monolithic Phase Locked Loop (PLL) based clock generator designed for telecommuni-

cations systems operating at 2.5Gb/s. The VSC8121 incorporates a reactance-based (LC) Voltage Controlled

Oscillator (VCO) with low phase noise. The PLL’s loop filter is on-chip.

The device has a differential 2.488GHz CML clock output (CO/CON) signal, a single-ended TTL low-

speed clock (LSCLK) output equivalent in frequency to that of the reference clock, and a TTL reference clock

input selectable for 51.84MHz, 77.76MHz or 155.52MHz. TTL inputs REFSEL[0:1] are used to make this

selection.

A clean REFCLK signal is required since jitter below the PLL loop bandwidth, which is present on the

REFCLK input, will appear on the output. Jitter on REFCLK at frequencies above the loop bandwidth will be

attenuated by the PLL. The state of REFSEL[0:1] will select which frequency is expected on the REFCLK

input.

VSC8121 Functional Block Diagram

• Monolithic Phase Locked Loop

• On-Chip LC Oscillator

• On-Chip Loop Filter

• TTL/CMOS Reference Clock

• Selectable Reference

• Jitter Meets SONET OC-48 and

SDH STM-16 Requirements

• High-Speed CML Clock Output

• Single 3.3V Supply

• Compact 10mm x 10mm 44 Pin PQFP Package

REFCLK

LSCLK

CO

CON

Ph.Freq.

Detector

Loop

Filter

CLOCK

OUT

VCO

Divider

REFSEL[0:1]