ISL9440CIRZ datasheet(21/25 Pages) RENESAS

21 / 25 page

ISL9440B, ISL9440C

FN6799 Rev 4.00

Page 21 of 25

February 18, 2016

The linear regulator output can be supplied by the output of

one of the PWMs. When using a PFET, the output of the linear

regulator will track the PWM supply after the PWM output rises

to a voltage greater than the threshold of the PFET pass

device. The voltage differential between the PWM and the

linear output will be the load current times the rDS(ON).

Base-Drive Noise Reduction

The high-impedance base driver is susceptible to system

noise, especially when the linear regulator is lightly loaded.

Capacitively coupled switching noise or inductively coupled

EMI onto the base drive causes fluctuations in the base

current, which appear as noise on the linear regulator’s output.

Keep the base drive traces away from the step-down

converter, and as short as possible, to minimize noise

coupling. A resistor in series with the gate drivers reduces the

switching noise generated by PWM. Additionally, a bypass

capacitor may be placed across the base-to-emitter resistor.

This bypass capacitor, in addition to the transistor’s input

capacitor, could bring in a second pole that will destabilize the

linear regulator. Therefore, the stability requirements determine

the maximum base-to-emitter capacitance.

Layout Guidelines

Careful attention to layout requirements is necessary for

successful implementation of an ISL9440B and ISL9440C

based DC/DC converter. The ISL9440B and ISL9440C switch

at a very high frequency and therefore, the switching times are

very short. At these switching frequencies, even the shortest

trace has significant impedance. Also, the peak gate drive

current rises significantly in an extremely short time. Transition

speed of the current from one device to another causes

voltage spikes across the interconnecting impedances and

parasitic circuit elements. These voltage spikes can degrade

efficiency, generate EMI, increase device overvoltage stress

and ringing. Careful component selection and proper PC board

layout minimizes the magnitude of these voltage spikes.

There are three sets of critical components in a DC/DC

converter using the ISL9440B and ISL9440C: the controller,

the switching power components and the small signal

components. The switching power components are the most

critical from a layout point of view because they switch a large

amount of energy so they tend to generate a large amount of

noise. The critical small signal components are those

connected to sensitive nodes or those supplying critical bias

currents. A multi-layer printed circuit board is recommended.

Layout Considerations

1. The Input capacitors, Upper FET, Lower FET, Inductor and

Output capacitor should be placed first. Isolate these power

components on the topside of the board with their ground

terminals adjacent to one another. Place the input high

frequency decoupling ceramic capacitor very close to the

MOSFETs.

2. Use separate ground planes for power ground and small

signal ground. Connect the SGND and PGND together

close to the IC. Do not connect them together anywhere

else.

3. The loop formed by Input capacitor, the top FET and the

bottom FET must be kept as small as possible.

4. Ensure the current paths from the input capacitor to the

MOSFET, to the output inductor and output capacitor are as

short as possible with maximum allowable trace widths.

5. Place The PWM controller IC close to lower FET. The

LGATE connection should be short and wide. The IC can be

best placed over a quiet ground area. Avoid switching

ground loop current in this area.

6. Place VCC_5V bypass capacitor very close to VCC_5V pin

of the IC and connect its ground to the PGND plane.

7. Place the gate drive components BOOT diode and BOOT

capacitors together near controller IC.

8. The output capacitors should be placed as close to the load

as possible. Use short wide copper regions to connect

output capacitors-to-load to avoid inductance and

resistances.

9. Use copper filled polygons or wide but short trace to

connect the junction of upper FET, Lower FET and output

inductor. Also keep the PHASE node connection to the IC

short. Do not unnecessarily oversize the copper islands for

PHASE node. Since the phase nodes are subjected to very

high dv/dt voltages, the stray capacitor formed between

these islands and the surrounding circuitry will tend to

couple switching noise.

10. Route all high speed switching nodes away from the control

circuitry.

11. Create a separate small analog ground plane near the IC.

Connect the SGND pin to this plane. All small signal

grounding paths including feedback resistors, current limit

setting resistors and ENx pull-down resistors should be

connected to this SGND plane.

12. Separate current sensing traces from PHASE node

connections

13. Ensure the feedback connection to the output capacitor is

short and direct.

Component Selection Guidelines

MOSFET Considerations

The logic level MOSFETs are chosen for optimum efficiency

given the potentially wide input voltage range and output power

requirements. Two N-Channel MOSFETs are used in each of

the synchronous-rectified buck converters for the 3 PWM

outputs. These MOSFETs should be selected based upon

rDS(ON), gate supply requirements, and thermal management

considerations.

The power dissipation includes two loss components;

conduction loss and switching loss. These losses are

distributed between the upper and lower MOSFETs according

to duty cycle (see Equations 11 and 12). The conduction

losses are the main component of power dissipation for the

lower MOSFETs. Only the upper MOSFET has significant

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