ISL78310 datasheet(12/14 Pages) RENESAS

12 / 14 page

ISL78310

FN7810 Rev 2.00

Page 12 of 14

November 7, 2014

Power Dissipation

The junction temperature must not exceed the range specified in

the “Recommended Operating Conditions” on page 5. The power

dissipation can be calculated by using Equation 6:

The maximum allowed junction temperature, TJ(MAX), and the

maximum expected ambient temperature, TA(MAX), will

determine the maximum allowable power dissipation, as shown

in Equation 7:

JA is the junction-to-ambient thermal resistance.

For safe operation, ensure that the power dissipation PD,

calculated from Equation 6, is less than the maximum allowable

power dissipation PD(MAX).

Heatsinking the DFN Package

The DFN package uses the copper area on the PCB as a heat-sink.

The EPAD of this package must be soldered to the copper plane

(GND plane) for heat sinking. Figure 17 shows a curve for the

JA

of the DFN package for different copper area sizes.

General Power PAD Design

Considerations

Figure 18 shows the recommended use of vias on the thermal

pad to remove heat from the IC. This typical array populates the

thermal pad footprint with vias spaced three times the radius

distance from the center of each via. Small via size is advisable,

but not to the extent that solder reflow becomes difficult.

All vias should be connected to the pad potential, with low

thermal resistance for efficient heat transfer. Complete

connection of the plated-through hole to each plane is important.

It is not recommended to use “thermal relief” patterns to connect

the vias.

VIN VOUT

–

 I

OUT

VIN IGND



(EQ. 6)

PDMAX



TJMAX

 TA

–

 



(EQ. 7)

FIGURE 17. 3mmx3mm 10 LD DFN ON 4-LAYER PCB WITH THERMAL

VIAS

JA vs EPAD-MOUNT COPPER LAND AREA ON PCB

EPAD-MOUNT COPPER LAND AREA ON PCB, mm2

FIGURE 18. PCB VIA PATTERN

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