ICL7106, ICL7107, ICL7107S

FN3082 Rev 9.00

Page 6 of 17

October 24, 2014

Detailed Description

Analog Section

Figure 3 shows the analog section for the ICL7106 and ICL7107.

Each measurement cycle is divided into three phases. They are

(1) auto-zero (A-Z), (2) signal integrate (INT) and (3) deintegrate

(DE).

Auto-Zero Phase

During auto-zero three things happen. First, input high and low are

disconnected from the pins and internally shorted to analog

COMMON. Second, the reference capacitor is charged to the

reference voltage. Third, a feedback loop is closed around the

offset voltages in the buffer amplifier, integrator, and comparator.

Since the comparator is included in the loop, the A-Z accuracy is

limited only by the noise of the system. In any case, the offset

referred to the input is less than 10µV.

Signal Integrate Phase

During signal integrate, the auto-zero loop is opened, the internal

short is removed, and the internal input high and low are connected

to the external pins. The converter then integrates the differential

voltage between IN HI and IN LO for a fixed time. This differential

voltage can be within a wide common mode range: up to 1V from

either supply. If, on the other hand, the input signal has no return

with respect to the converter power supply, IN LO can be tied to

analog COMMON to establish the correct common mode voltage. At

the end of this phase, the polarity of the integrated signal is

determined.

Deintegrate Phase

The final phase is deintegrate, or reference integrate. Input low is

internally connected to analog COMMON and input high is

connected across the previously charged reference capacitor.

Circuitry within the chip ensures that the capacitor will be

connected with the correct polarity to cause the integrator output

to return to zero. The time required for the output to return to zero

is proportional to the input signal. Specifically the digital reading

displayed is:

Differential Input

The input can accept differential voltages anywhere within the

common mode range of the input amplifier, or specifically from

0.5V below the positive supply to 1V above the negative supply. In

this range, the system has a CMRR of 86dB typical. However, care

must be exercised to assure the integrator output does not

saturate. A worst case condition would be a large positive common

mode voltage with a near full scale negative differential input

voltage. The negative input signal drives the integrator positive

when most of its swing has been used up by the positive common

mode voltage. For these critical applications the integrator output

swing can be reduced to less than the recommended 2V full scale

swing with little loss of accuracy. The integrator output can swing

to within 0.3V of either supply without loss of linearity.

Differential Reference

The reference voltage can be generated anywhere within the power

supply voltage of the converter. The main source of common mode

error is a roll-over voltage caused by the reference capacitor losing or

gaining charge to stray capacity on its nodes. If there is a large

common mode voltage, the reference capacitor can gain charge

(increase voltage) when called up to deintegrate a positive signal but

lose charge (decrease voltage) when called up to deintegrate a

negative input signal. This difference in reference for positive or

negative input voltage will give a roll-over error. However, by

selecting the reference capacitor such that it is large enough in

comparison to the stray capacitance, this error can be held to less

than 0.5 count worst case. (see “Component Value Selection” on

page 10.)

DISPLAY COUNT = 1000

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





(EQ. 1)

FIGURE 3. ANALOG SECTION OF ICL7106 AND ICL7107

DE

-

DE+

BUFFER

A-Z

INT

-

+

A-Z

COMPARATOR

IN HI

COMMON

IN LO

31

32

30

DE-

DE+

INT

A-Z

34

36

REF HI

REF LO

35

A-Z

A-Z

33

28

29

27

TO

DIGITAL

SECTION

A-Z AND DE(±)

INTEGRATOR

INT

STRAY

STRAY

V+

10

A

V-

N

INPUT

HIGH

2.8V

6.2V

V+

1

INPUT

LOW

-

+

-

+

-

+