DSPIC30F6014 datasheet(31/222 Pages) MICROCHIP

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 2004 Microchip Technology Inc.

Preliminary

DS70117C-page 29

dsPIC30F6011/6012/6013/6014

3.2

Data Address Space

The core has two data spaces. The data spaces can be

considered either separate (for some DSP instruc-

tions), or as one unified linear address range (for MCU

instructions). The data spaces are accessed using two

Address Generation Units (AGUs) and separate data

paths.

3.2.1

DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and

Y data space. A key element of this architecture is that

Y space is a subset of X space, and is fully contained

within X space. In order to provide an apparent linear

addressing space, X and Y spaces have contiguous

addresses.

When executing any instruction other than one of the

MAC

class of instructions, the X block consists of the 64-

Kbyte data address space (including all Y addresses).

When executing one of the MAC class of instructions,

the X block consists of the 64-Kbyte data address

space excluding the Y address block (for data reads

only). In other words, all other instructions regard the

entire data memory as one composite address space.

The MAC class instructions extract the Y address space

from data space and address it using EAs sourced from

W10 and W11. The remaining X data space is

addressed using W8 and W9. Both address spaces are

concurrently accessed only with the MAC class

instructions.

The data space memory maps are shown in Figure 3-8

and Figure 3-9.

3.2.2

DATA SPACES

The X data space is used by all instructions and sup-

ports all Addressing modes. There are separate read

and write data buses. The X read data bus is the return

data path for all instructions that view data space as

combined X and Y address space. It is also the X

address space data path for the dual operand read

instructions (MAC class). The X write data bus is the

only write path to data space for all instructions.

The X data space also supports modulo addressing for

all instructions, subject to Addressing mode restric-

tions. Bit-reversed addressing is only supported for

writes to X data space.

The Y data space is used in concert with the X data

space by the MAC class of instructions (CLR,

ED,

EDAC,

MAC,

MOVSAC,

MPY,

MPY.N

and MSC) to

provide two concurrent data read paths. No writes

occur across the Y bus. This class of instructions dedi-

cates two W register pointers, W10 and W11, to always

address Y data space, independent of X data space,

whereas W8 and W9 always address X data space.

Note that during accumulator write back, the data

address space is considered a combination of X and Y

data spaces, so the write occurs across the X bus.

Consequently, the write can be to any address in the

entire data space.

The Y data space can only be used for the data pre-

fetch operation associated with the MAC class of

instructions. It also supports modulo addressing for

automated circular buffers. Of course, all other instruc-

tions can access the Y data address space through the

X data path as part of the composite linear space.

The boundary between the X and Y data spaces is

defined as shown in Figure 3-8 and Figure 3-8 and is

not user programmable. Should an EA point to data

outside its own assigned address space, or to a loca-

tion outside physical memory, an all zero word/byte will

be returned. For example, although Y address space is

visible by all non-MAC instructions using any Address-

ing mode, an attempt by a MAC instruction to fetch data

from that space using W8 or W9 (X space pointers) will

return 0x0000.

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