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X5001PIZ Datasheet(PDF) 13 Page - Renesas Technology Corp

Part # X5001PIZ
Description  CPU Supervisor
PDF  20 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

X5001PIZ Datasheet(HTML) 13 Page - Renesas Technology Corp

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X5001
FN8125 Rev 1.00
Page 13 of 20
May 30, 2006
Data Output Timing
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Figure 10. Data Output Timing
Figure 11. Data Input Timing
Symbol
Parameter
1.8V-3.6V
2.7V-5.5V
Unit
Min.
Max.
Min.
Max.
fSCK
Clock frequency
0
1
0
2
MHz
tDIS
Output disable time
400
200
ns
tV
Output valid from clock low
400
200
ns
tHO
Output hold time
0
0
ns
tRO(3)
Output rise time
300
150
ns
tFO(3)
Output fall time
300
150
ns
SCK
CS
SO
SI
MSB Out
MSB–1 Out
LSB Out
ADDR
LSB IN
tCYC
tV
tHO
tWL
tWH
tDIS
tLAG
SCK
CS
SI
SO
MSB In
tSU
tRI
tLAG
tLEAD
tH
LSB In
tCS
tFI
High Impedance



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