SA25C020LEMLFF datasheet(21/31 Pages) ETC

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SA25C020 Advanced Information

SAIFUN

Write Status Register (WRSR)

The WRSR instruction enables the user to

select one of four levels of protection. The

SA25C020 is divided into four array

segments. The top quarter, top half or all of

the memory segments can be protected

(for more details, refer to Table 8). The

data within a selected segment is therefore

read-only.

Table 8. Block Write Protect Bits

Status Register Bits

Level

BP1

BP0

Array Addresses

Protected

None

1/4

30000 - 3FFFF

1/2

20000 - 3FFFF

All

00000 - 3FFFF

The WRSR instruction (as shown in

Table 9) also allows the user to enable or

disable the WPb pin via the WPBEN bit.

Hardware write protection is enabled when

the WPb pin is low and the WPBEN bit is

1, and disabled when either the WP pin is

high or the WPBEN bit is 0. When the

device is hardware write protected, writes

to the status register are disabled.

NOTE:

When the WPBEN bit is hardware write

protected, it cannot be changed back

to 0 while the WPb pin is held low.

Table 9. WPBEN Operation

WPb WPBEN WEN

Protected

Blocks

Un-

protected

Blocks

Status

Protected

Protected Protected

Protected

Writeable Writeable

Low

Protected

Protected Protected

Low

Protected

Writeable Protected

High

Protected

Protected Protected

High

Protected

Writeable Writeable

The WRSR instruction is enabled:

1. When the WPb pin is held high

and

the

device

has

been

previously write enabled via the

WREN instruction.

2. When the WPb pin is held low, the

WPBEN bit is 0 and the device

has been previously write enabled

via the WREN instruction.

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