ZL2005P datasheet(28/41 Pages) RENESAS

28 / 41 page

ZL2005P

FN6849 Rev 3.00

Page 28 of 41

December 16, 2011

The current limit threshold can be set via the I2C/SMBus

interface. Please refer to Application Note AN2013 for

further details on setting current limit parameters.

5.10 Loop Compensation

The ZL2005P operates as a voltage-mode synchronous

buck controller with a fixed frequency PWM scheme.

Although the ZL2005P uses a digital control loop, it

operates much like a traditional analog PWM controller.

See Figure 19 for a simplified block diagram of the

ZL2005P control loop, which differs from an analog

control loop by the constants in the PWM and compen-

sation blocks. As in the analog controller case, the com-

pensation block compares the output voltage to the

desired voltage reference and compensation zeros are

added to keep the loop stable. The resulting integrated

error signal is used to drive the PWM logic, converting

the error signal into a duty cycle value to drive the exter-

nal MOSFETs.

Figure 19. Control Loop Block Diagram

In the ZL2005P, the compensation zeros are set by con-

figuring the FC0 pin or via the I2C/SMBus interface

once the user has calculated the required settings. Most

applications can be served by using the pin-strap com-

pensation settings listed in Table 24. These settings will

yield a conservative crossover frequency. The parame-

ters of the feedback compensation can also be set using

the I2C/SMBus interface. A sofware (CompZLTM) is

also available from Zilker Labs to calculate automati-

cally the compensation parameters.

FC1 pin is not used in the ZL2005P.

Table 24. Pin-Strap Setting for Loop

Compensation

5.11 Non-Linear Response Settings

The ZL2005P incorporates a non-linear response (NLR)

loop that decreases the response time and the output

voltage deviation in the event of a sudden output load

current step. The NLR loop incorporates a secondary

error signal processing path that bypasses the primary

error loop when the output begins to transition outside of

the standard regulation limits. This scheme results in a

higher equivalent loop bandwidth than is possible using

a traditional linear loop.

When a load current step function imposed on the output

causes the output voltage to drop below the lower regu-

lation limit, the NLR circuitry will force a positive cor-

rection signal that will turn on the upper MOSFET and

quickly force the output to increase. A negative load step

will cause the NLR circuitry to force a negative correc-

tion signal that will turn on the lower MOSFET and

quickly force the output to decrease.

5.12 Efficiency Optimized Driver Dead-time

Control

The ZL2005P utilizes a closed loop algorithm to opti-

mize the dead-time applied between the gate drive sig-

nals for the top and bottom FETs. In a synchronous buck

converter, the MOSFET drive circuitry must be designed

such that the top and bottom MOSFETs are never in the

conducting state at the same time. (Potentially damaging

currents flow in the circuit if both top and bottom MOS-

FETs are simultaneously on for periods of time exceed-

ing a few nanoseconds.) Conversely, long periods of

time in which both MOSFETs are off reduce overall cir-

cuit efficiency by allowing current to flow in their para-

sitic body diodes.

30 mV

17.8 k



85 mV

51.1 k



35 mV

19.6 k



90 mV

56.2 k



40 mV

21.5 k



95 mV

61.9 k



45 mV

23.7 k



100 mV

68.1 k



50 mV

26.1 k



Table 23. Current Limit Threshold Voltage

Settings

1-D

VIN

VOUT

DPWM

Compensation

FC0 Pin

Description

HIGH

High Q, Low Bandwidth

OPEN

Real zeros, High Bandwidth

LOW

Low Q, Low Bandwidth

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